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Instruction Set Architecture » History » Version 15

Alexander Kamkin, 03/17/2023 03:21 PM

1 1 Alexander Protsenko
h1. Instruction Set Architecture
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3 13 Alexander Protsenko
{font-weight:bold; background:#ddd}. | Section | Subsection | Specified instruction |
4 14 Alexander Protsenko
{background:#cfc}. |/6.  "Data processing - immediate":https://forge.ispras.ru/projects/microtesk-arm-demo/wiki/Instruction_Set_Architecture#Data-processing-immediate | Arithmetic (immediate) | 12 |
5 13 Alexander Protsenko
{background:#cfc}. | Logical (immediate)| 10|
6
{background:#cfc}. | Move (wide immediate)| 6|
7
{background:#cfc}. | Move (immediate)| 6|
8
{background:#cfc}. | PC-relative address calculation| 2|
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{background:#cfc}. | Extract register| 2|
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{font-weight:bold; background:#ddd}. |\2. Total: | 38 |
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{background:#cfc}. |/6.  "Data processing - register":https://forge.ispras.ru/projects/microtesk-arm-demo/wiki/Instruction_Set_Architecture#Data-processing-register | Arithmetic (shifted register) | 12 |
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{background:#cfc}. | Arithmetic (extending register) | 12 |
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{background:#cfc}. | Logical (shifted register) | 20 |
14
{background:#cfc}. | Move (register) | 4 |
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{background:#cfc}. | Multiply and divide | 18 |
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{background:#cfc}. | Divide | 4 |
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{font-weight:bold; background:#ddd}. |\2. Total: | 70 |
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{background:#cfc}. |/8.  "Branches, Exception generation, and System instructions":https://forge.ispras.ru/projects/microtesk-arm-demo/wiki/Instruction_Set_Architecture#Branches-Exception-generation-and-System-instructions | Conditional branch | 7 |
19 13 Alexander Protsenko
{background:#cfc}. | Unconditional branch (immediate) | 2 |
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{background:#cfc}. | Unconditional branch (register) | 3 |
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{background:#cfc}. | Exception generation and return | 10 |
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{background:#cfc}. | System register instructions | 6 |
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{background:#cfc}. | System instructions | 8 |
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{background:#cfc}. | Hint instructions | 7 |
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{background:#cfc}. | Barriers and CLREX instructions| 4 |
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{font-weight:bold; background:#ddd}. |\2. Total: | 47 |
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{background:#cfc}. |/3.  "Loads and stores":https://forge.ispras.ru/projects/microtesk-arm-demo/wiki/Instruction_Set_Architecture#Loads-and-stores | Load/store register | 2 |
28 13 Alexander Protsenko
{background:#cfc}. | Load-Exclusive/Store-Exclusive | 12 |
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{background:#cfc}. | Load-Acquire/Store-Release | 20 |
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{font-weight:bold; background:#ddd}. |\2. Total: | 34 |
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32 3 Alexander Protsenko
h2. Data processing - immediate
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h3. Arithmetic (immediate)
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### ADD (immediate). Add.
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Specification: add, add_32
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### SUB (immediate). Subtract.
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Specification: sub, sub_32
40
### ADDS (immediate). Add and set flags.
41
Specification: adds, adds_32
42
### SUBS (immediate). Subtract and set flags.
43
Specification: subs, subs_32
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### CMP (immediate). Compare.
45
Specification: cmp, cmp_32
46
### CMN (immediate). Compare negative.
47
Specification: cmn, cmn_32
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49 12 Alexander Protsenko
+Total:+ 12.
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h3. Logical (immediate)
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53
### AND (immediate). Bitwise AND
54
Specification: and_bitmask, and_bitmask_32
55
### ANDS (immediate). Bitwise AND and set flags
56
Specification: ands_bitmask, ands_bitmask_32
57
### EOR (immediate). Bitwise exclusive OR
58
Specification: eor_bitmask, eor_bitmask_32
59
### ORR (immediate). Bitwise inclusive OR
60
Specification: orr_bitmask, orr_bitmask_32
61
### TST (immediate). TST Test bits
62
Specification: tst_bitmask, tst_bitmask_32
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+Total:+ 10.
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h3. Move (wide immediate)
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### MOVZ. Move wide with zero
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Specification: movz, movz_32
70
### MOVN. Move wide with NOT
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Specification: movn, movn_32
72
### MOVK. Move wide with keep
73
Specification: movk, movk_32
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+Total:+ 6.
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h3. Move (immediate)
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### MOV (wide immediate). Move (wide immediate)
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Specification: mov_wide_imm, mov_wide_imm_32
81
### MOV (inverted wide immediate). Move (inverted wide immediate)
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Specification: mov_inv_wide_imm, mov_inv_wide_imm_32
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### MOV (bitmask immediate). Move (bitmask immediate)
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Specification: mov_bitmask, mov_bitmask_32
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+Total:+ 6.
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h3. PC-relative address calculation
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90
### ADRP. Compute address of 4KB page at a PC-relative offset
91
Specification: adrp
92
### ADR. Compute address of label at a PC-relative offset.
93
Specification: adr
94
95 12 Alexander Protsenko
+Total:+ 2.
96
97 3 Alexander Protsenko
h3. Extract register
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99
### EXTR. Extract register from pair
100
Specification: extr, extr_32
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102 12 Alexander Protsenko
+Total:+ 2.
103
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h2. Data processing - register
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106
h3. Arithmetic (shifted register)
107
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### ADD (shifted register). Add
109
Specification: add_sh_reg, add_sh_reg_32
110
### ADDS (shifted register). Add and set flags
111
Specification: adds_sh_reg, adds_sh_reg_32
112
### SUB (shifted register). Subtract
113
Specification: sub_sh_reg, sub_sh_reg_32
114
### SUBS (shifted register). Subtract and set flags
115
Specification: subs_sh_reg, subs_sh_reg_32
116
### CMN (shifted register). Compare negative
117
Specification: cmn_sh_reg, cmn_sh_reg_32
118
### CMP (shifted register). Compare
119
Specification: cmp_sh_reg, cmp_sh_reg_32
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121 12 Alexander Protsenko
+Total:+ 12.
122
123 3 Alexander Protsenko
h3. Arithmetic (extending register)
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125
### ADD (extended register). Add
126
Specification: add_ex_reg, add_ex_reg_32
127
### ADDS (extended register). Add and set flags
128
Specification: adds_ex_reg, adds_ex_reg_32
129
### SUB (extended register). Subtract
130
Specification: sub_ex_reg, sub_ex_reg_32
131
### SUBS (extended register). Subtract and set flags
132
Specification: subs_ex_reg, subs_ex_reg_32
133
### CMN (extended register). Compare negative
134
Specification: cmn_ex_reg, cmn_ex_reg_32
135
### CMP (extended register). Compare
136
Specification: cmp_ex_reg, cmp_ex_reg_32
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138 12 Alexander Protsenko
+Total:+ 12.
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140 1 Alexander Protsenko
h3. Logical (shifted register)
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142 4 Alexander Protsenko
### AND (shifted register). Bitwise AND
143
Specification: and_bitwise, and_bitwise_32
144
### ANDS (shifted register). Bitwise AND and set flags
145
Specification: ands_bitwise, ands_bitwise_32
146
### BIC (shifted register). Bitwise bit clear
147
Specification: bic_bitwise, bic_bitwise_32
148
### BICS (shifted register). Bitwise bit clear and set flags
149
Specification: bics_bitwise, bics_bitwise_32
150
### EON (shifted register). Bitwise exclusive OR NOT
151
Specification: eon_bitwise, eon_bitwise_32
152
### EOR (shifted register). Bitwise exclusive OR
153
Specification: eor_bitwise, eor_bitwise_32
154
### ORR (shifted register). Bitwise inclusive OR
155
Specification: orr_bitwise, orr_bitwise_32
156
### MVN. Bitwise NOT
157
Specification: mvn_bitwise, mvn_bitwise_32
158
### ORN (shifted register). Bitwise inclusive OR NOT
159
Specification: orn_bitwise, orn_bitwise_32
160
### TST (shifted register). Test bits
161
Specification: tst_bitwise, tst_bitwise_32
162
163 12 Alexander Protsenko
+Total:+ 20.
164
165 4 Alexander Protsenko
h3. Move (register)
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167
###  MOV (register). Move register
168
Specification: mov_reg, mov_reg_32
169
### MOV (to/from SP). Move register to SP or move SP to register
170
Specification: mov_sp, mov_sp_32
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+Total:+ 4.
173
174 5 Alexander Protsenko
h3. Multiply and divide
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###  MADD. Multiply-add
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Specification: madd, madd_32
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###  MSUB. Multiply-subtract
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Specification: msub, msub_32
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###  MNEG. Multiply-negate
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Specification: mneg, mneg_32
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###  MUL. Multiply
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Specification: mul, mul_32
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###  SMADDL. Signed multiply-add long
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Specification: smaddl
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###  SMSUBL. Signed multiply-subtract long
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Specification: smsubl
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###  SMNEGL. Signed multiply-negate long
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Specification: smnegl
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###  SMULL. Signed multiply long
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Specification: smull
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###  SMULH. Signed multiply high
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Specification: smulh
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###  UMADDL. Unsigned multiply-add long
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Specification: umaddl
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###  UMSUBL. Unsigned multiply-subtract long
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Specification: umsubl
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###  UMNEGL. Unsigned multiply-negate long
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Specification: umnegl
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###  UMULL. Unsigned multiply long
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Specification: umull
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###  UMULH. Unsigned multiply high
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Specification: umulh
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205 12 Alexander Protsenko
+Total:+ 18.
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h3. Divide
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209 6 Alexander Protsenko
###  SDIV. Signed divide
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Specification: sdiv, sdiv_32
211
###  UDIV. Unsigned divide
212
Specification: udiv, udiv_32
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214 12 Alexander Protsenko
+Total:+ 4.
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h2. Branches, Exception generation, and System instructions
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218 7 Alexander Protsenko
h3. Conditional Branch
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###  B.cond. Branch conditionally
221
Specification: b
222
### CBNZ. Compare and branch if nonzero
223
Specification: cbnz, cbnz_32
224
### CBZ. Compare and branch if zero
225
Specification: cbz, cbz_32
226
### TBNZ. Test bit and branch if nonzero
227
Specification: tbnz
228
### TBZ. Test bit and branch if zero
229
Specification: tbz
230
231 12 Alexander Protsenko
+Total:+ 7.
232
233 7 Alexander Protsenko
h3. Unconditional branch (immediate)
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### B. Branch unconditionally
236
Specification: b_imm
237
### BL. Branch with link
238
Specification: bl
239
240 12 Alexander Protsenko
+Total:+ 2.
241
242 7 Alexander Protsenko
h3. Unconditional branch (register)
243
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### BLR. Branch with link to register
245
Specification: blr
246
### BR. Branch to register
247
Specification: br
248
### RET. Return from subroutine
249
Specification: ret
250
251 12 Alexander Protsenko
+Total:+ 3.
252
253 7 Alexander Protsenko
h3. Exception generation and return
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*Exception generation*
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257 7 Alexander Protsenko
### BRK. Breakpoint Instruction
258
Specification: brk
259
### HLT. Halt Instruction HLT
260
Specification: hlt
261
### HVC. Generate exception targeting Exception level 2 HVC
262
Specification: hvc
263
### SMC. Generate exception targeting Exception level 3 SMC
264
Specification: smc
265
### SVC. Generate exception targeting Exception level 1
266
Specification: svc
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268 12 Alexander Protsenko
+Total:+ 5.
269
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*Exception return*
271
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### ERET. Exception return using current ELR and SPSR
273
Specification: eret
274
275 12 Alexander Protsenko
+Total:+ 1.
276
277 8 Alexander Protsenko
*Debug state*
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### DCPS1. Debug switch to Exception level 1 DCPS1
280
Specification: dcps1
281
### DCPS2. Debug switch to Exception level 2 DCPS2
282
Specification: dcps2
283
### DCPS3. Debug switch to Exception level 3 DCPS3
284
Specification: dcps3
285
### DRPS. Debug restore PE state
286
Specification: drps
287
288 12 Alexander Protsenko
+Total:+ 4.
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h3. System register instructions
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### MRS. Move System register to general-purpose register MRS
293
Specification: msr
294
### MSR. Move general-purpose register to System register MSR (register)
295
Specification: mrs
296
### MSR. Move immediate to PE state field MSR (immediate)
297
Specification: msr_dc, msr_ds, msr_ss, msr_uao
298
299 12 Alexander Protsenko
+Total:+ 6.
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h3. System instructions
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### SYS. System instruction
304
Specification: sys
305
### SYSL. System instruction with result
306
Specification: sysl
307
### IC. Instruction cache maintenance
308
Specification: ic, ic_reg
309
### DC. Data cache maintenance
310
Specification: dc
311
### AT. Address translation
312
Specification: at
313
### TLBI. TLB Invalidate
314
Specification: tlbi, tlbi_reg
315
316 12 Alexander Protsenko
+Total:+ 8.
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h3. Hint instructions
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### NOP. No operation
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Specification: nop
322 1 Alexander Protsenko
### YIELD. Yield hint
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Specification: yield_op
324 1 Alexander Protsenko
### WFE. Wait for event
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Specification: wfe
326 1 Alexander Protsenko
### WFI. Wait for interrupt
327 9 Alexander Protsenko
Specification: wfi
328 1 Alexander Protsenko
### SEV. Send event
329 9 Alexander Protsenko
Specification: sev
330 1 Alexander Protsenko
### SEVL. Send event local
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Specification: sevl
332 1 Alexander Protsenko
### HINT. Unallocated hint
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Specification: hint
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335 12 Alexander Protsenko
+Total:+ 7.
336
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h3. Barriers and CLREX instructions
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### CLREX. Clear Exclusives monitor
340
Specification: clrex
341
### DMB. Data memory barrier
342
Specification: dmb
343
### DSB. Data synchronization barrier
344
Specification: dsb
345
### ISB. Instruction synchronization barrier
346
Specification: isb
347
348 12 Alexander Protsenko
+Total:+ 4.
349
350 9 Alexander Protsenko
h2. Loads and stores
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352
h3. Load/store register
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### LDR. Load register (immediate offset)
355
Specification: ldr_postindex
356
### STR. Store register (immediate offset)
357
Specification: str_postindex
358
359 12 Alexander Protsenko
+Total:+ 2.
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361 11 Alexander Protsenko
h3. Load-Exclusive/Store-Exclusive
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### LDXR. Load Exclusive register
364
Specification: ldxr, ldxr_32
365
### LDXRB. Load Exclusive byte
366
Specification: ldxrb_32
367
### LDXRH. Load Exclusive halfword
368
Specification: ldxrh_32
369
### LDXP. Load Exclusive pair
370
Specification: ldxp, ldxp_32
371
### STXR. Store Exclusive register
372
Specification: stxr, stxr_32
373
### STXRB. Store Exclusive byte
374
Specification: stxrb_32
375
### STXRH. Store Exclusive halfword
376
Specification: stxrh_32
377
### STXP. Store Exclusive pair
378
Specification: stxp, stxp_32
379
380 12 Alexander Protsenko
+Total:+ 12.
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h3. Load-Acquire/Store-Release
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384
*Non-exclusive Load-Acquire and Store-Release instructions*
385
386
### LDAR. Load-Acquire Register
387
Specification: ldar, ldar_32
388
### LDARB. Load-Acquire Byte
389
Specification: ldarb
390
### LDARH. Load-Acquire Halfword
391
Specification: ldarh
392
### STLR. Store-Release Register
393
Specification: stlr, stlr_32
394
### STLRB. Store-Release Byte
395
Specification: stlrb
396
### STLRH. Store-Release Halfword
397
Specification: stlrh
398
399 12 Alexander Protsenko
+Total:+ 8.
400
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*Exclusive Load-Acquire and Store-Release instructions*
402
403
### LDAXR. Load-Acquire Exclusive register
404
Specification: ldaxr, ldaxr_32
405
### LDAXRB. Load-Acquire Exclusive byte
406
Specification: ldaxrb_32
407
### LDAXRH. Load-Acquire Exclusive halfword
408
Specification: ldaxrh_32
409
### LDAXP. Load-Acquire Exclusive pair
410
Specification: ldaxp, ldaxp_32
411
### STLXR. Store-Release Exclusive register
412
Specification: stlxr, stlxr_32
413
### STLXRB. Store-Release Exclusive byte
414
Specification: stlxrb_32
415
### STLXRH. Store-Release Exclusive halfword
416
Specification: stlxrh_32
417
### STLXP. Store-Release Exclusive pair
418
Specification: stlxp, stlxp_32
419
420
+Total:+ 12.
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422 10 Alexander Protsenko
h2. Pseudo instructions
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424 10 Alexander Protsenko
psldr, psldr32
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426
+Total:+ 2.