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## Instruction Set Architecture » History » Revision 14

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Alexander Protsenko, 03/16/2023 06:10 PM

# Instruction Set Architecture¶

 Section Subsection Specified instruction Data processing - immediate Arithmetic (immediate) 12 Logical (immediate) 10 Move (wide immediate) 6 Move (immediate) 6 PC-relative address calculation 2 Extract register 2 Total: 38 Data processing - register Arithmetic (shifted register) 12 Arithmetic (extending register) 12 Logical (shifted register) 20 Move (register) 4 Multiply and divide 18 Divide 4 Total: 70 Branches, Exception generating, and System instructions Conditional Branch 7 Unconditional branch (immediate) 2 Unconditional branch (register) 3 Exception generation and return 10 System register instructions 6 System instructions 8 Hint instructions 7 Barriers and CLREX instructions 4 Total: 47 Loads and stores Load/store register 2 Load-Exclusive/Store-Exclusive 12 Load-Acquire/Store-Release 20 Total: 34

## Data processing - immediate¶

### Arithmetic (immediate)¶

2. SUB (immediate). Subtract.
Specification: sub, sub_32
4. SUBS (immediate). Subtract and set flags.
Specification: subs, subs_32
5. CMP (immediate). Compare.
Specification: cmp, cmp_32
6. CMN (immediate). Compare negative.
Specification: cmn, cmn_32

Total: 12.

### Logical (immediate)¶

1. AND (immediate). Bitwise AND
2. ANDS (immediate). Bitwise AND and set flags
3. EOR (immediate). Bitwise exclusive OR
4. ORR (immediate). Bitwise inclusive OR
5. TST (immediate). TST Test bits

Total: 10.

### Move (wide immediate)¶

1. MOVZ. Move wide with zero
Specification: movz, movz_32
2. MOVN. Move wide with NOT
Specification: movn, movn_32
3. MOVK. Move wide with keep
Specification: movk, movk_32

Total: 6.

### Move (immediate)¶

1. MOV (wide immediate). Move (wide immediate)
Specification: mov_wide_imm, mov_wide_imm_32
2. MOV (inverted wide immediate). Move (inverted wide immediate)
Specification: mov_inv_wide_imm, mov_inv_wide_imm_32

Total: 6.

Total: 2.

### Extract register¶

1. EXTR. Extract register from pair
Specification: extr, extr_32

Total: 2.

## Data processing - register¶

### Arithmetic (shifted register)¶

3. SUB (shifted register). Subtract
Specification: sub_sh_reg, sub_sh_reg_32
4. SUBS (shifted register). Subtract and set flags
Specification: subs_sh_reg, subs_sh_reg_32
5. CMN (shifted register). Compare negative
Specification: cmn_sh_reg, cmn_sh_reg_32
6. CMP (shifted register). Compare
Specification: cmp_sh_reg, cmp_sh_reg_32

Total: 12.

### Arithmetic (extending register)¶

3. SUB (extended register). Subtract
Specification: sub_ex_reg, sub_ex_reg_32
4. SUBS (extended register). Subtract and set flags
Specification: subs_ex_reg, subs_ex_reg_32
5. CMN (extended register). Compare negative
Specification: cmn_ex_reg, cmn_ex_reg_32
6. CMP (extended register). Compare
Specification: cmp_ex_reg, cmp_ex_reg_32

Total: 12.

### Logical (shifted register)¶

1. AND (shifted register). Bitwise AND
Specification: and_bitwise, and_bitwise_32
2. ANDS (shifted register). Bitwise AND and set flags
Specification: ands_bitwise, ands_bitwise_32
3. BIC (shifted register). Bitwise bit clear
Specification: bic_bitwise, bic_bitwise_32
4. BICS (shifted register). Bitwise bit clear and set flags
Specification: bics_bitwise, bics_bitwise_32
5. EON (shifted register). Bitwise exclusive OR NOT
Specification: eon_bitwise, eon_bitwise_32
6. EOR (shifted register). Bitwise exclusive OR
Specification: eor_bitwise, eor_bitwise_32
7. ORR (shifted register). Bitwise inclusive OR
Specification: orr_bitwise, orr_bitwise_32
8. MVN. Bitwise NOT
Specification: mvn_bitwise, mvn_bitwise_32
9. ORN (shifted register). Bitwise inclusive OR NOT
Specification: orn_bitwise, orn_bitwise_32
10. TST (shifted register). Test bits
Specification: tst_bitwise, tst_bitwise_32

Total: 20.

### Move (register)¶

1. MOV (register). Move register
Specification: mov_reg, mov_reg_32
2. MOV (to/from SP). Move register to SP or move SP to register
Specification: mov_sp, mov_sp_32

Total: 4.

### Multiply and divide¶

2. MSUB. Multiply-subtract
Specification: msub, msub_32
3. MNEG. Multiply-negate
Specification: mneg, mneg_32
4. MUL. Multiply
Specification: mul, mul_32
6. SMSUBL. Signed multiply-subtract long
Specification: smsubl
7. SMNEGL. Signed multiply-negate long
Specification: smnegl
8. SMULL. Signed multiply long
Specification: smull
9. SMULH. Signed multiply high
Specification: smulh
11. UMSUBL. Unsigned multiply-subtract long
Specification: umsubl
12. UMNEGL. Unsigned multiply-negate long
Specification: umnegl
13. UMULL. Unsigned multiply long
Specification: umull
14. UMULH. Unsigned multiply high
Specification: umulh

Total: 18.

### Divide¶

1. SDIV. Signed divide
Specification: sdiv, sdiv_32
2. UDIV. Unsigned divide
Specification: udiv, udiv_32

Total: 4.

## Branches, Exception generating, and System instructions¶

### Conditional Branch¶

1. B.cond. Branch conditionally
Specification: b
2. CBNZ. Compare and branch if nonzero
Specification: cbnz, cbnz_32
3. CBZ. Compare and branch if zero
Specification: cbz, cbz_32
4. TBNZ. Test bit and branch if nonzero
Specification: tbnz
5. TBZ. Test bit and branch if zero
Specification: tbz

Total: 7.

### Unconditional branch (immediate)¶

1. B. Branch unconditionally
Specification: b_imm
Specification: bl

Total: 2.

### Unconditional branch (register)¶

1. BLR. Branch with link to register
Specification: blr
2. BR. Branch to register
Specification: br
3. RET. Return from subroutine
Specification: ret

Total: 3.

### Exception generation and return¶

Exception generating

1. BRK. Breakpoint Instruction
Specification: brk
2. HLT. Halt Instruction HLT
Specification: hlt
3. HVC. Generate exception targeting Exception level 2 HVC
Specification: hvc
4. SMC. Generate exception targeting Exception level 3 SMC
Specification: smc
5. SVC. Generate exception targeting Exception level 1
Specification: svc

Total: 5.

Exception return

1. ERET. Exception return using current ELR and SPSR
Specification: eret

Total: 1.

Debug state

1. DCPS1. Debug switch to Exception level 1 DCPS1
Specification: dcps1
2. DCPS2. Debug switch to Exception level 2 DCPS2
Specification: dcps2
3. DCPS3. Debug switch to Exception level 3 DCPS3
Specification: dcps3
4. DRPS. Debug restore PE state
Specification: drps

Total: 4.

### System register instructions¶

1. MRS. Move System register to general-purpose register MRS
Specification: msr
2. MSR. Move general-purpose register to System register MSR (register)
Specification: mrs
3. MSR. Move immediate to PE state field MSR (immediate)
Specification: msr_dc, msr_ds, msr_ss, msr_uao

Total: 6.

### System instructions¶

1. SYS. System instruction
Specification: sys
2. SYSL. System instruction with result
Specification: sysl
3. IC. Instruction cache maintenance
Specification: ic, ic_reg
4. DC. Data cache maintenance
Specification: dc
Specification: at
6. TLBI. TLB Invalidate
Specification: tlbi, tlbi_reg

Total: 8.

### Hint instructions¶

1. NOP. No operation
Specification: nop
2. YIELD. Yield hint
Specification: yield_op
3. WFE. Wait for event
Specification: wfe
4. WFI. Wait for interrupt
Specification: wfi
5. SEV. Send event
Specification: sev
6. SEVL. Send event local
Specification: sevl
7. HINT. Unallocated hint
Specification: hint

Total: 7.

### Barriers and CLREX instructions¶

1. CLREX. Clear Exclusives monitor
Specification: clrex
2. DMB. Data memory barrier
Specification: dmb
3. DSB. Data synchronization barrier
Specification: dsb
4. ISB. Instruction synchronization barrier
Specification: isb

Total: 4.

1. LDR. Load register (immediate offset)
Specification: ldr_postindex
2. STR. Store register (immediate offset)
Specification: str_postindex

Total: 2.

Specification: ldxr, ldxr_32
Specification: ldxrb_32
Specification: ldxrh_32
Specification: ldxp, ldxp_32
5. STXR. Store Exclusive register
Specification: stxr, stxr_32
6. STXRB. Store Exclusive byte
Specification: stxrb_32
7. STXRH. Store Exclusive halfword
Specification: stxrh_32
8. STXP. Store Exclusive pair
Specification: stxp, stxp_32

Total: 12.

Specification: ldar, ldar_32
Specification: ldarb
Specification: ldarh
4. STLR. Store-Release Register
Specification: stlr, stlr_32
5. STLRB. Store-Release Byte
Specification: stlrb
6. STLRH. Store-Release Halfword
Specification: stlrh

Total: 8.

Specification: ldaxr, ldaxr_32
Specification: ldaxrb_32
Specification: ldaxrh_32
Specification: ldaxp, ldaxp_32
5. STLXR. Store-Release Exclusive register
Specification: stlxr, stlxr_32
6. STLXRB. Store-Release Exclusive byte
Specification: stlxrb_32
7. STLXRH. Store-Release Exclusive halfword
Specification: stlxrh_32
8. STLXP. Store-Release Exclusive pair
Specification: stlxp, stlxp_32

Total: 12.

## Pseudo instructions¶

psldr, psldr32

Total: 2.

Updated by Alexander Protsenko over 1 year ago · 14 revisions