Instruction Set Architecture¶

Data processing - immediate¶

Arithmetic (immediate)¶

1. ADD (immediate). Add.
   Specification: add, add_32
2. SUB (immediate). Subtract.
   Specification: sub, sub_32
3. ADDS (immediate). Add and set flags.
   Specification: adds, adds_32
4. SUBS (immediate). Subtract and set flags.
   Specification: subs, subs_32
5. CMP (immediate). Compare.
   Specification: cmp, cmp_32
6. CMN (immediate). Compare negative.
   Specification: cmn, cmn_32

Logical (immediate)¶

1. AND (immediate). Bitwise AND
   Specification: and_bitmask, and_bitmask_32
2. ANDS (immediate). Bitwise AND and set flags
   Specification: ands_bitmask, ands_bitmask_32
3. EOR (immediate). Bitwise exclusive OR
   Specification: eor_bitmask, eor_bitmask_32
4. ORR (immediate). Bitwise inclusive OR
   Specification: orr_bitmask, orr_bitmask_32
5. TST (immediate). TST Test bits
   Specification: tst_bitmask, tst_bitmask_32

Move (wide immediate)¶

1. MOVZ. Move wide with zero
   Specification: movz, movz_32
2. MOVN. Move wide with NOT
   Specification: movn, movn_32
3. MOVK. Move wide with keep
   Specification: movk, movk_32

Move (immediate)¶

1. MOV (wide immediate). Move (wide immediate)
   Specification: mov_wide_imm, mov_wide_imm_32
2. MOV (inverted wide immediate). Move (inverted wide immediate)
   Specification: mov_inv_wide_imm, mov_inv_wide_imm_32
3. MOV (bitmask immediate). Move (bitmask immediate)
   Specification: mov_bitmask, mov_bitmask_32

PC-relative address calculation¶

1. ADRP. Compute address of 4KB page at a PC-relative offset
   Specification: adrp
2. ADR. Compute address of label at a PC-relative offset.
   Specification: adr

Extract register¶

1. EXTR. Extract register from pair
   Specification: extr, extr_32

Data processing - register¶

Arithmetic (shifted register)¶

1. ADD (shifted register). Add
   Specification: add_sh_reg, add_sh_reg_32
2. ADDS (shifted register). Add and set flags
   Specification: adds_sh_reg, adds_sh_reg_32
3. SUB (shifted register). Subtract
   Specification: sub_sh_reg, sub_sh_reg_32
4. SUBS (shifted register). Subtract and set flags
   Specification: subs_sh_reg, subs_sh_reg_32
5. CMN (shifted register). Compare negative
   Specification: cmn_sh_reg, cmn_sh_reg_32
6. CMP (shifted register). Compare
   Specification: cmp_sh_reg, cmp_sh_reg_32

Arithmetic (extending register)¶

1. ADD (extended register). Add
   Specification: add_ex_reg, add_ex_reg_32
2. ADDS (extended register). Add and set flags
   Specification: adds_ex_reg, adds_ex_reg_32
3. SUB (extended register). Subtract
   Specification: sub_ex_reg, sub_ex_reg_32
4. SUBS (extended register). Subtract and set flags
   Specification: subs_ex_reg, subs_ex_reg_32
5. CMN (extended register). Compare negative
   Specification: cmn_ex_reg, cmn_ex_reg_32
6. CMP (extended register). Compare
   Specification: cmp_ex_reg, cmp_ex_reg_32

Logical (shifted register)¶

1. AND (shifted register). Bitwise AND
   Specification: and_bitwise, and_bitwise_32
2. ANDS (shifted register). Bitwise AND and set flags
   Specification: ands_bitwise, ands_bitwise_32
3. BIC (shifted register). Bitwise bit clear
   Specification: bic_bitwise, bic_bitwise_32
4. BICS (shifted register). Bitwise bit clear and set flags
   Specification: bics_bitwise, bics_bitwise_32
5. EON (shifted register). Bitwise exclusive OR NOT
   Specification: eon_bitwise, eon_bitwise_32
6. EOR (shifted register). Bitwise exclusive OR
   Specification: eor_bitwise, eor_bitwise_32
7. ORR (shifted register). Bitwise inclusive OR
   Specification: orr_bitwise, orr_bitwise_32
8. MVN. Bitwise NOT
   Specification: mvn_bitwise, mvn_bitwise_32
9. ORN (shifted register). Bitwise inclusive OR NOT
   Specification: orn_bitwise, orn_bitwise_32
10. TST (shifted register). Test bits
    Specification: tst_bitwise, tst_bitwise_32

Move (register)¶

1. MOV (register). Move register
   Specification: mov_reg, mov_reg_32
2. MOV (to/from SP). Move register to SP or move SP to register
   Specification: mov_sp, mov_sp_32

[47]: madd
[48]: madd_32
[49]: msub
[50]: msub_32
[51]: mneg
[52]: mneg_32
[53]: mul
[54]: mul_32
[55]: smaddl
[56]: smsubl
[57]: smnegl
[58]: smull
[59]: smulh
[60]: umaddl
[61]: umsubl
[62]: umnegl
[63]: umull
[64]: umulh
[65]: sdiv
[66]: sdiv_32
[67]: udiv
[68]: udiv_32

[115]: b
[116]: cbnz
[117]: cbnz_32
[118]: cbz
[119]: cbz_32
[120]: tbnz
[121]: tbz
[122]: b_imm
[123]: bl
[124]: blr
[125]: br
[126]: ret
[127]: ldr_postindex
[128]: str_postindex
[129]: ldxr
[130]: ldxr_32
[131]: ldxrb_32
[132]: ldxrh_32
[133]: ldxp
[134]: ldxp_32
[135]: stxr
[136]: stxr_32
[137]: stxrb_32
[138]: stxrh_32
[139]: stxp
[140]: stxp_32
[141]: ldar
[142]: ldar_32
[143]: ldarb
[144]: ldarh
[145]: stlr
[146]: stlr_32
[147]: stlrb
[148]: stlrh
[149]: ldaxr
[150]: ldaxr_32
[151]: ldaxrb_32
[152]: ldaxrh_32
[153]: ldaxp
[154]: ldaxp_32
[155]: stlxr
[156]: stlxr_32
[157]: stlxrb_32
[158]: stlxrh_32
[159]: stlxp
[160]: stlxp_32
[161]: svc
[162]: hvc
[163]: smc
[164]: eret
[165]: brk
[166]: hlt
[167]: dcps1
[168]: dcps2
[169]: dcps3
[170]: drps
[171]: mrs
[172]: msr
[173]: msr_dc
[174]: msr_ds
[175]: msr_ss
[176]: msr_uao
[177]: sys
[178]: sysl
[179]: ic
[180]: ic_reg
[181]: dc
[182]: at
[183]: tlbi
[184]: tlbi_reg
[185]: hint
[186]: nop
[187]: yield_op
[188]: wfe
[189]: wfi
[190]: sev
[191]: sevl
[192]: clrex
[193]: dsb
[194]: dmb
[195]: isb

[200]: psldr
[201]: psldr32