Instruction Set Architecture¶

Arithmetic (immediate)¶

1. ADD (immediate). Add.
   Specification: add, add_32
2. SUB (immediate). Subtract.
   Specification: sub, sub_32
3. ADDS (immediate). Add and set flags.
   Specification: adds, adds_32
4. SUBS (immediate). Subtract and set flags.
   Specification: subs, subs_32
5. CMP (immediate). Compare.
   Specification: cmp, cmp_32
6. CMN (immediate). Compare negative.
   Specification: cmn, cmn_32

[2]: mov_sp
[3]: mov_sp_32

Logical (immediate)¶

1. AND (immediate). Bitwise AND
   Specification: and_bitmask, and_bitmask_32
2. ANDS (immediate). Bitwise AND and set flags
   Specification: ands_bitmask, ands_bitmask_32
3. EOR (immediate). Bitwise exclusive OR
   Specification: eor_bitmask, eor_bitmask_32
4. ORR (immediate). Bitwise inclusive OR
   Specification: orr_bitmask, orr_bitmask_32
5. TST (immediate). TST Test bits
   Specification: tst_bitmask, tst_bitmask_32

Move (wide immediate)¶

1. MOVZ. Move wide with zero
   Specification: movz, movz_32
2. MOVN. Move wide with NOT
   Specification: movn, movn_32
3. MOVK. Move wide with keep
   Specification: movk, movk_32

Move (immediate)¶

1. MOV (wide immediate). Move (wide immediate)
   Specification: mov_wide_imm, mov_wide_imm_32
2. MOV (inverted wide immediate). Move (inverted wide immediate)
   Specification: mov_inv_wide_imm, mov_inv_wide_imm_32
3. MOV (bitmask immediate). Move (bitmask immediate)
   Specification: mov_bitmask, mov_bitmask_32

[43]: adrp
[44]: adr
[45]: extr
[46]: extr_32
[47]: madd
[48]: madd_32
[49]: msub
[50]: msub_32
[51]: mneg
[52]: mneg_32
[53]: mul
[54]: mul_32
[55]: smaddl
[56]: smsubl
[57]: smnegl
[58]: smull
[59]: smulh
[60]: umaddl
[61]: umsubl
[62]: umnegl
[63]: umull
[64]: umulh
[65]: sdiv
[66]: sdiv_32
[67]: udiv
[68]: udiv_32
[69]: add_sh_reg
[70]: add_sh_reg_32
[71]: adds_sh_reg
[72]: adds_sh_reg_32
[73]: sub_sh_reg
[74]: sub_sh_reg_32
[75]: subs_sh_reg
[76]: subs_sh_reg_32
[77]: cmn_sh_reg
[78]: cmn_sh_reg_32
[79]: cmp_sh_reg
[80]: cmp_sh_reg_32
[81]: add_ex_reg
[82]: add_ex_reg_32
[83]: adds_ex_reg
[84]: adds_ex_reg_32
[85]: sub_ex_reg
[86]: sub_ex_reg_32
[87]: subs_ex_reg
[88]: subs_ex_reg_32
[89]: cmn_ex_reg
[90]: cmn_ex_reg_32
[91]: cmp_ex_reg
[92]: cmp_ex_reg_32
[93]: and_bitwise
[94]: and_bitwise_32
[95]: ands_bitwise
[96]: ands_bitwise_32
[97]: bic_bitwise
[98]: bic_bitwise_32
[99]: bics_bitwise
[100]: bics_bitwise_32
[101]: eon_bitwise
[102]: eon_bitwise_32
[103]: eor_bitwise
[104]: eor_bitwise_32
[105]: orr_bitwise
[106]: orr_bitwise_32
[107]: orn_bitwise
[108]: orn_bitwise_32
[109]: mvn_bitwise
[110]: mvn_bitwise_32
[111]: mov_reg
[112]: mov_reg_32
[113]: tst_bitwise
[114]: tst_bitwise_32
[115]: b
[116]: cbnz
[117]: cbnz_32
[118]: cbz
[119]: cbz_32
[120]: tbnz
[121]: tbz
[122]: b_imm
[123]: bl
[124]: blr
[125]: br
[126]: ret
[127]: ldr_postindex
[128]: str_postindex
[129]: ldxr
[130]: ldxr_32
[131]: ldxrb_32
[132]: ldxrh_32
[133]: ldxp
[134]: ldxp_32
[135]: stxr
[136]: stxr_32
[137]: stxrb_32
[138]: stxrh_32
[139]: stxp
[140]: stxp_32
[141]: ldar
[142]: ldar_32
[143]: ldarb
[144]: ldarh
[145]: stlr
[146]: stlr_32
[147]: stlrb
[148]: stlrh
[149]: ldaxr
[150]: ldaxr_32
[151]: ldaxrb_32
[152]: ldaxrh_32
[153]: ldaxp
[154]: ldaxp_32
[155]: stlxr
[156]: stlxr_32
[157]: stlxrb_32
[158]: stlxrh_32
[159]: stlxp
[160]: stlxp_32
[161]: svc
[162]: hvc
[163]: smc
[164]: eret
[165]: brk
[166]: hlt
[167]: dcps1
[168]: dcps2
[169]: dcps3
[170]: drps
[171]: mrs
[172]: msr
[173]: msr_dc
[174]: msr_ds
[175]: msr_ss
[176]: msr_uao
[177]: sys
[178]: sysl
[179]: ic
[180]: ic_reg
[181]: dc
[182]: at
[183]: tlbi
[184]: tlbi_reg
[185]: hint
[186]: nop
[187]: yield_op
[188]: wfe
[189]: wfi
[190]: sev
[191]: sevl
[192]: clrex
[193]: dsb
[194]: dmb
[195]: isb

[200]: psldr
[201]: psldr32