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Alexander Kamkin

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04/01/2020

10:23 AM MicroTESK Task #10193 (New): Cache instances configuration
MMU specifications look like they are written for a single core. That's OK and, I think, it should be so. However, it... Alexander Kamkin
09:56 AM MicroTESK Task #10168 (Resolved): Support for Write-Back policy in cache specification
Alexander Kamkin
09:56 AM MicroTESK Task #10178 (Resolved): Support for basic cache coherence protocols in MMU specifications
Alexander Kamkin

03/31/2020

05:39 PM Deductive Verification Tool for Machine Code artifact.zip
Alexander Kamkin

03/30/2020

09:04 PM MicroTESK Bug #10188 (Resolved): CacheUnitTestCase fails for exclusive caches
Alexander Kamkin
10:08 AM Fortress Bug #10177: TreeVisitor's SKIP status does not work as expected
IMHO, the status should be re-set automatically. Alexander Kamkin

03/26/2020

12:19 PM MicroTESK Bug #10188: CacheUnitTestCase fails for exclusive caches
# Reallocation should start only if no copies left.
# Intermediate caches should not allocate data if the target one...
Alexander Kamkin
11:50 AM MicroTESK Bug #10188 (Resolved): CacheUnitTestCase fails for exclusive caches
Exclusiveness property is violated:... Alexander Kamkin
11:03 AM MicroTESK Bug #10187 (Resolved): testWriteThroughAllocationInclusive: lw core=2, address=d058: deadbeef != a8c7e6ae
Alexander Kamkin

03/25/2020

10:16 PM MicroTESK Bug #10187: testWriteThroughAllocationInclusive: lw core=2, address=d058: deadbeef != a8c7e6ae
The situation is as follows:
* lw core=3
* lw core=0
* sw core=3
* lw core=2
It seems that Write-Through doe...
Alexander Kamkin

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