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Instruction Set Architecture¶

 Section Subsection Specified instruction Data processing - immediate Arithmetic (immediate) 12 Logical (immediate) 10 Move (wide immediate) 6 Move (immediate) 6 PC-relative address calculation 2 Extract register 2 In total: 38 Data processing - register Arithmetic (shifted register) 12 Arithmetic (extending register) 12 Logical (shifted register) 20 Move (register) 4 Multiply and divide 18 Divide 4 In total: 70 Branches, Exception generation, and System instructions Conditional branch 7 Unconditional branch (immediate) 2 Unconditional branch (register) 3 Exception generation and return 10 System register instructions 6 System instructions 8 Hint instructions 7 Barriers and CLREX instructions 4 In total: 47 Loads and stores Load/store register 2 Load-Exclusive/Store-Exclusive 12 Load-Acquire/Store-Release 20 In total: 34

Data processing - immediate¶

Arithmetic (immediate)¶

2. SUB (immediate). Subtract.
Specifications: sub, sub_32
4. SUBS (immediate). Subtract and set flags.
Specifications: subs, subs_32
5. CMP (immediate). Compare.
Specifications: cmp, cmp_32
6. CMN (immediate). Compare negative.
Specifications: cmn, cmn_32

In total: 12.

Logical (immediate)¶

1. AND (immediate). Bitwise AND
2. ANDS (immediate). Bitwise AND and set flags
3. EOR (immediate). Bitwise exclusive OR
4. ORR (immediate). Bitwise inclusive OR
5. TST (immediate). TST Test bits

In total: 10.

Move (wide immediate)¶

1. MOVZ. Move wide with zero
Specifications: movz, movz_32
2. MOVN. Move wide with NOT
Specifications: movn, movn_32
3. MOVK. Move wide with keep
Specifications: movk, movk_32

In total: 6.

Move (immediate)¶

1. MOV (wide immediate). Move (wide immediate)
Specifications: mov_wide_imm, mov_wide_imm_32
2. MOV (inverted wide immediate). Move (inverted wide immediate)
Specifications: mov_inv_wide_imm, mov_inv_wide_imm_32

In total: 6.

In total: 2.

Extract register¶

1. EXTR. Extract register from pair
Specifications: extr, extr_32

In total: 2.

Data processing - register¶

Arithmetic (shifted register)¶

3. SUB (shifted register). Subtract
Specifications: sub_sh_reg, sub_sh_reg_32
4. SUBS (shifted register). Subtract and set flags
Specifications: subs_sh_reg, subs_sh_reg_32
5. CMN (shifted register). Compare negative
Specifications: cmn_sh_reg, cmn_sh_reg_32
6. CMP (shifted register). Compare
Specifications: cmp_sh_reg, cmp_sh_reg_32

In total: 12.

Arithmetic (extending register)¶

3. SUB (extended register). Subtract
Specifications: sub_ex_reg, sub_ex_reg_32
4. SUBS (extended register). Subtract and set flags
Specifications: subs_ex_reg, subs_ex_reg_32
5. CMN (extended register). Compare negative
Specifications: cmn_ex_reg, cmn_ex_reg_32
6. CMP (extended register). Compare
Specifications: cmp_ex_reg, cmp_ex_reg_32

In total: 12.

Logical (shifted register)¶

1. AND (shifted register). Bitwise AND
Specifications: and_bitwise, and_bitwise_32
2. ANDS (shifted register). Bitwise AND and set flags
Specifications: ands_bitwise, ands_bitwise_32
3. BIC (shifted register). Bitwise bit clear
Specifications: bic_bitwise, bic_bitwise_32
4. BICS (shifted register). Bitwise bit clear and set flags
Specifications: bics_bitwise, bics_bitwise_32
5. EON (shifted register). Bitwise exclusive OR NOT
Specifications: eon_bitwise, eon_bitwise_32
6. EOR (shifted register). Bitwise exclusive OR
Specifications: eor_bitwise, eor_bitwise_32
7. ORR (shifted register). Bitwise inclusive OR
Specifications: orr_bitwise, orr_bitwise_32
8. MVN. Bitwise NOT
Specifications: mvn_bitwise, mvn_bitwise_32
9. ORN (shifted register). Bitwise inclusive OR NOT
Specifications: orn_bitwise, orn_bitwise_32
10. TST (shifted register). Test bits
Specifications: tst_bitwise, tst_bitwise_32

In total: 20.

Move (register)¶

1. MOV (register). Move register
Specifications: mov_reg, mov_reg_32
2. MOV (to/from SP). Move register to SP or move SP to register
Specifications: mov_sp, mov_sp_32

In total: 4.

Multiply and divide¶

2. MSUB. Multiply-subtract
Specifications: msub, msub_32
3. MNEG. Multiply-negate
Specifications: mneg, mneg_32
4. MUL. Multiply
Specifications: mul, mul_32
6. SMSUBL. Signed multiply-subtract long
Specifications: smsubl
7. SMNEGL. Signed multiply-negate long
Specifications: smnegl
8. SMULL. Signed multiply long
Specifications: smull
9. SMULH. Signed multiply high
Specifications: smulh
11. UMSUBL. Unsigned multiply-subtract long
Specifications: umsubl
12. UMNEGL. Unsigned multiply-negate long
Specifications: umnegl
13. UMULL. Unsigned multiply long
Specifications: umull
14. UMULH. Unsigned multiply high
Specifications: umulh

In total: 18.

Divide¶

1. SDIV. Signed divide
Specifications: sdiv, sdiv_32
2. UDIV. Unsigned divide
Specifications: udiv, udiv_32

In total: 4.

Branches, Exception generation, and System instructions¶

Conditional Branch¶

1. B.cond. Branch conditionally
Specifications: b
2. CBNZ. Compare and branch if nonzero
Specifications: cbnz, cbnz_32
3. CBZ. Compare and branch if zero
Specifications: cbz, cbz_32
4. TBNZ. Test bit and branch if nonzero
Specifications: tbnz
5. TBZ. Test bit and branch if zero
Specifications: tbz

In total: 7.

Unconditional branch (immediate)¶

1. B. Branch unconditionally
Specifications: b_imm
Specifications: bl

In total: 2.

Unconditional branch (register)¶

1. BLR. Branch with link to register
Specifications: blr
2. BR. Branch to register
Specifications: br
3. RET. Return from subroutine
Specifications: ret

In total: 3.

Exception generation and return¶

Exception generation

1. BRK. Breakpoint Instruction
Specifications: brk
2. HLT. Halt Instruction HLT
Specifications: hlt
3. HVC. Generate exception targeting Exception level 2 HVC
Specifications: hvc
4. SMC. Generate exception targeting Exception level 3 SMC
Specifications: smc
5. SVC. Generate exception targeting Exception level 1
Specifications: svc

In total: 5.

Exception return

1. ERET. Exception return using current ELR and SPSR
Specifications: eret

In total: 1.

Debug state

1. DCPS1. Debug switch to Exception level 1 DCPS1
Specifications: dcps1
2. DCPS2. Debug switch to Exception level 2 DCPS2
Specifications: dcps2
3. DCPS3. Debug switch to Exception level 3 DCPS3
Specifications: dcps3
4. DRPS. Debug restore PE state
Specifications: drps

In total: 4.

System register instructions¶

1. MRS. Move System register to general-purpose register MRS
Specifications: msr
2. MSR. Move general-purpose register to System register MSR (register)
Specifications: mrs
3. MSR. Move immediate to PE state field MSR (immediate)
Specifications: msr_dc, msr_ds, msr_ss, msr_uao

In total: 6.

System instructions¶

1. SYS. System instruction
Specifications: sys
2. SYSL. System instruction with result
Specifications: sysl
3. IC. Instruction cache maintenance
Specifications: ic, ic_reg
4. DC. Data cache maintenance
Specifications: dc
Specifications: at
6. TLBI. TLB Invalidate
Specifications: tlbi, tlbi_reg

In total: 8.

Hint instructions¶

1. NOP. No operation
Specifications: nop
2. YIELD. Yield hint
Specifications: yield_op
3. WFE. Wait for event
Specifications: wfe
4. WFI. Wait for interrupt
Specifications: wfi
5. SEV. Send event
Specifications: sev
6. SEVL. Send event local
Specifications: sevl
7. HINT. Unallocated hint
Specifications: hint

In total: 7.

Barriers and CLREX instructions¶

1. CLREX. Clear Exclusives monitor
Specifications: clrex
2. DMB. Data memory barrier
Specifications: dmb
3. DSB. Data synchronization barrier
Specifications: dsb
4. ISB. Instruction synchronization barrier
Specifications: isb

In total: 4.

1. LDR. Load register (immediate offset)
Specifications: ldr_postindex
2. STR. Store register (immediate offset)
Specifications: str_postindex

In total: 2.

Specifications: ldxr, ldxr_32
Specifications: ldxrb_32
Specifications: ldxrh_32
Specifications: ldxp, ldxp_32
5. STXR. Store Exclusive register
Specifications: stxr, stxr_32
6. STXRB. Store Exclusive byte
Specifications: stxrb_32
7. STXRH. Store Exclusive halfword
Specifications: stxrh_32
8. STXP. Store Exclusive pair
Specifications: stxp, stxp_32

In total: 12.

Specifications: ldar, ldar_32
Specifications: ldarb
Specifications: ldarh
4. STLR. Store-Release Register
Specifications: stlr, stlr_32
5. STLRB. Store-Release Byte
Specifications: stlrb
6. STLRH. Store-Release Halfword
Specifications: stlrh

In total: 8.

Specifications: ldaxr, ldaxr_32
Specifications: ldaxrb_32
Specifications: ldaxrh_32
Specifications: ldaxp, ldaxp_32
5. STLXR. Store-Release Exclusive register
Specifications: stlxr, stlxr_32
6. STLXRB. Store-Release Exclusive byte
Specifications: stlxrb_32
7. STLXRH. Store-Release Exclusive halfword
Specifications: stlxrh_32
8. STLXP. Store-Release Exclusive pair
Specifications: stlxp, stlxp_32

In total: 12.

Pseudo instructions¶

psldr, psldr32

In total: 2.

Updated by Alexander Kamkin over 1 year ago · 17 revisions