Verilog Translator

In the ru.ispras.verilog.parser.sample.DataMemTestCase log the following record appears:

DEBUG: Reduce: (BVEXTRACT 0 7 mem_access_addr)

It comes from the following fragment of the Verilog '_data_mem.v_' module:

wire [`DATA_MEM_ADDR_WIDTH-1 : 0] ram_addr = mem_access_addr[`DATA_MEM_ADDR_WIDTH-1 : 0];

The Fortress node that is created from the right hand side expression of this assignment is incorrect, because the first param of BVEXTRACT operation should be greater or equal to the second one.