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0.1

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Features: grammar, parser, AST, traverser, printer

91%

194 issues   (177 closed — 17 open)

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Bug

131/143
Feature

4/4
Developer Request

1/1
Task

41/46
Related issues
Bug #4107: Support for pulse control in specparam assignment Actions
Bug #4110: AST_DECLARATION: adding delay for net declarations Actions
Bug #4124: Support for port attributes in a module's signature Actions
Bug #4965: Привязывание переменных к их декларациям Actions
Bug #4997: Неправильно работают конструкции: replication, concatenation Actions
Bug #5028: Не обрабатывается конструкция repeat Actions
Bug #5086: Исключение при вычислении константных выражений Actions
Bug #5121: Похоже, что x- и z-маски всегда нулевые Actions
Bug #5163: Конец файла после директивы препроцессора Actions
Bug #5164: После директивы `endif в той же строчке могут идти лексемы Actions
Bug #5165: Verilog static checker raises NullPointerException on test 005 Actions
Bug #5492: retrascope + sapic.v = java.lang.IllegalStateException: Operand is not a constant integer value: 00000000000000000000000000000011 Actions
Bug #5567: VerilogStaticChecker.ExpressionVisitor is not abstract and does not override abstract method getOperandOrder() in ExprTreeVisitor Actions
Bug #6355: src/test/verilog/fifo/fifo_testbench.v: NullPointerException Actions
Bug #6363: src/test/verilog/fifo0/mem_2p.v: AbstractMethodError Actions
Bug #7098: src/test/verilog/mips16/data_mem.v: 'mem_access_addr' has null declaration Actions
Bug #7474: missing empty branches for 'if' statements Actions
Bug #8726: Cannot find the module declaration inside the module Actions
Bug #8738: DataMemTestCase falls with error Actions
Bug #8739: VerilogStaticChecker causes an exception when handling variables with parameter-defined length Actions
Bug #8740: Use VerilogGenerateProcessor in VerilogElaborator Actions
Bug #8747: defparam uses paths, not identifiers as it is implied in the grammar Actions
Bug #8755: Elaborator does not apply port connections Actions
Bug #8779: mips16/data_mem.v: wrong type for define-containing declaration of 'ram_addr' wire Actions
Bug #8786: ru.ispras.verilog.parser.sample.FifoTestbenchTestCase fails Actions
Bug #8789: Error when using special symbols in strings Actions
Bug #8791: Error when using escaped identifiers Actions
Bug #8793: Error when using attributes Actions
Bug #8796: Error when handling incorrect tokens under ifdef Actions
Bug #8797: Error when using multiple includes Actions
Bug #8801: NullPointerException in vcegar-benchmarks/pi_bus Actions
Bug #8802: ClassCastException in vcegar-benchmarks/miim Actions
Bug #8803: Error in parsing the specify construct Actions
Bug #8804: Exception when dividing 4-bit vector by 32-bit one Actions
Bug #8808: Module not found in vcegar-benchmarks/ipbdp Actions
Bug #8827: vcegar-benchmarks/mpeg_1.v fails with IllegalArgumentException Actions
Bug #8828: vcegar-benchmarks/pi_bus fails with IndexOutOfBoundsException Actions
Bug #8829: vcegar-benchmarks/usb_phy fails with IllegalArgumentException Actions
Bug #8830: verilog2smv-vis-benchmarks/Silver-bcu fails with IllegalArgumentException Actions
Bug #8831: vcegar-benchmarks/ipbdp/ipbdp_hier.v: java.lang.IllegalArgumentException: Bit vector sizes do not match: 4 != 32. Actions
Bug #8832: verilog/opencores/mips16/IF_stage.v: java.lang.IllegalStateException: Parameter is not a value: (BVSUB 8 1) Actions
Bug #8833: Error when building AST for if-generate constructs without else branches Actions
Bug #8846: test_19_04_00_3.v: Module 'real_last' cannot be found Actions
Bug #8847: test_17_01_01_2_1.v: Module 'pulldown' cannot be found Actions
Bug #8848: test_07_08_00_1.v: Module 'pullup' cannot be found Actions
Bug #8849: VerilogIeeeTestCase.runTest_04_10_01_1 [floating point parameters]: java.lang.IllegalArgumentException Actions
Bug #8850: VerilogIeeeTestCase.runTest_05_01_14_1: java.lang.NullPointerException Actions
Bug #8851: VerilogIeeeTestCase.runTest_05_01_14_3: java.lang.IllegalArgumentException: 0 must be > 0 Actions
Bug #8852: VerilogIeeeTestCase.runTest_05_01_14_4: java.lang.NullPointerException Actions
Bug #8853: VerilogIeeeTestCase.runTest_05_02_01_2: java.lang.IllegalArgumentException Actions
Bug #8854: VerilogIeeeTestCase.runTest_05_02_02_2: java.lang.NullPointerException Actions
Bug #8855: VerilogIeeeTestCase.runTest_10_03_00_5: java.lang.IllegalArgumentException Actions
Bug #8856: VerilogIeeeTestCase.runTest_10_04_05_1: java.lang.IllegalArgumentException Actions
Bug #8857: VerilogIeeeTestCase.runTest_12_02_02_2_1: java.lang.NullPointerException Actions
Bug #8858: VerilogIeeeTestCase.runTest_12_04_01_2: java.lang.IllegalStateException: Parameter is not a value: (BVZEROEXT 2147483646 i) Actions
Bug #8859: VerilogIeeeTestCase.runTest_12_04_02_3: java.lang.NullPointerException Actions
Bug #8860: VerilogIeeeTestCase.runTest_12_04_02_4: java.lang.NullPointerException Actions
Bug #8861: VerilogIeeeTestCase.runTest_12_04_03_1: java.lang.IllegalStateException: BigInteger data is not convertible to Boolean. Actions
Bug #8862: VerilogIeeeTestCase.runTest_12_08_02_1: java.lang.IllegalArgumentException Actions
Bug #8863: VerilogIeeeTestCase.runTest_17_02_04_4_1: java.lang.IllegalArgumentException Actions
Bug #8864: VerilogIeeeTestCase.runTest_17_10_02_1_i: java.lang.IllegalArgumentException Actions
Bug #8865: VerilogIeeeTestCase.runTest_19_11_00_1: java.lang.IllegalArgumentException: Declaration=DECLARATION(), parent=MODULE(m2) Actions
Bug #8899: NullPointerException in verilog2smv-vis-benchmarks/FourByFour/two.v Actions
Bug #8957: wrong datatype for arrays Actions
Bug #8990: vcegar-benchmarks/pi_bus/main_1.v: incorrect translation of nested "if" conditions Actions
Bug #9055: Texas97IFetchVerilogPrinterTestCase: java.lang.IndexOutOfBoundsException: 4294967283 is out of bounds. Actions
Bug #9160: ru.ispras.verilog.parser.sample.Mips16CoreTopTestCase: Module 'mips_16_core_top' cannot be found Actions
Bug #9165: Incorrect parameter value calculation at hierarchical Verilog description Actions
Bug #9173: Incorrect DataType: BIT_VECTOR(1) instead of BIT_VECTOR(40) Actions
Bug #9174: NullPointerException via VerilogLiteral construction Actions
Bug #9182: ru.ispras.verilog.parser.sample.MulFifoTestCase: java.lang.IllegalStateException: Parameter is not a value: i Actions
Bug #9190: ru.ispras.verilog.parser.sample.DescriptorBuffersTestCase: incorrect calculation for string parameter values Actions
Bug #9202: ru.ispras.verilog.parser.sample.PjIcuIcctl1TestCase: java.lang.ArrayIndexOutOfBoundsException: 3 Actions
Bug #9209: java.util.EmptyStackException at ru.ispras.verilog.parser.util.TokenSourceStack.getLastParentToken(TokenSourceStack.java:70) Actions
Bug #9210: java.lang.IllegalArgumentException at ru.ispras.fortress.expression.Nodes.bvextract(Nodes.java:322) Actions
Bug #9211: java.lang.IllegalArgumentException at ru.ispras.verilog.parser.model.VerilogModule.addDeclaration(VerilogModule.java:193) Actions
Bug #9212: ru.ispras.verilog.parser.VerilogVisVerilog2SmvTestCase.runTest_Vlunc_vlunc: Module 'transform' cannot be found Actions
Bug #9213: ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PPC60X_bus_src_arbiter: Module 'ArbiterStatus' cannot be found Actions
Bug #9214: ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PPC60X_bus_src_cpu: Module 'AddressTenure' cannot be found Actions
Bug #9215: ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PPC60X_bus_src_mem: Module 'AddrStatus' cannot be found Actions
Bug #9222: ru.ispras.verilog.parser.VerilogVisVerilog2SmvTestCase.runTest_Sampleq_twoFifo1: java.lang.IllegalStateException: Parameter is not a value: LOGLENGTH Actions
Bug #9223: ru.ispras.verilog.parser.VerilogVcegarTestCase.runTest_pj_icu_icctl1: ERROR: Declaration of 'clk' has not been found Actions
Bug #9224: ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PCI_BUS_Verilog_MV_files_PCInorm: ERROR: Function declaration '$random' has not been found Actions
Bug #9225: ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_MPEG_prefixcode: ERROR: ../texas97-tests/MPEG/prefixcode.v line 70:8 no viable alternative at input ';' Actions
Bug #9226: ru.ispras.verilog.parser.VerilogVcegarTestCase.runTest_small_pipeline_pipeline_smv: /src/test/verilog/vcegar-tests/small/pipeline/pipeline_smv.v line 38:10 no viable alternative at input 'property' Actions
Bug #9229: VerilogIeeeTestCase.runTest_03_05_01_3: incorrect token under disabled if-def Actions
Bug #9230: ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PI_BUS_multi_master_bus: java.lang.IllegalArgumentException Actions
Bug #9231: ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PI_BUS_single_master_master2: java.lang.NullPointerException Actions
Bug #9239: ru.ispras.verilog.parser.sample.Mips16CoreTopTestCase: java.lang.IllegalArgumentException Actions
Bug #9250: ru.ispras.verilog.parser.sample.IfStageTestCase: src/test/verilog/rest-tests/mips16/IF_stage.v line 31:9 missing KW_BEGIN at 'pc' Actions
Bug #9252: ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_05_01_05_2: Cannot convert a real to a bitvector Actions
Bug #9253: ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_07_01_02_1: no viable alternative Actions
Bug #9254: ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_07_08_00_1: no viable alternative Actions
Bug #9255: ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_14_06_04_2_3: no viable alternative Actions
Bug #9256: ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_12_02_00_1: NullPointerException Actions
Bug #9257: ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_12_04_01_5: IllegalArgumentException Actions
Bug #9258: ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_12_04_02_1 STANDARD_OUT Actions
Bug #9259: ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_12_04_02_4: Task declaration has not been found Actions
Bug #9260: ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_10_02_02_1_2: StackOverflowError Actions
Bug #9261: ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_19_03_01_1: line 1:4 mismatched input ')' expecting LPAREN Actions
Bug #9262: ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_09_06_00_1: Descriptor has not been found Actions
Bug #9276: no errors returned for bug-with-macro-containing module Actions
Bug #9282: ru.ispras.verilog.parser.sample.DataMemTestCase: DEBUG: Reduce: (BVEXTRACT 0 7 mem_access_addr) Actions
Bug #9296: vcegar-tests/cache_coherence/two_processor_bin_2.v:46: illegal types of "then" and "else" expressions : unsigned word[1] and boolean Actions
Bug #9514: Net declaration assignment is a continuous assignment Actions
Bug #9594: extra 'BVEXTRACT' operation in right hand side expression in 'assign' block's statement Actions
Bug #9773: ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_10_04_03_1: ru.ispras.fortress.expression.NodeOperation cannot be cast to ru.ispras.fortress.expression.NodeValue Actions
Bug #9775: ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_10_04_04_1: Conversion = ''' Actions
Bug #9784: mul_fifo.v: wrong Fortress-based node representation of assignment left-hand side Actions
Bug #9798: ru.ispras.verilog.parser.sample.Bug9798TestCase: incorrect BVEXTRACT params for bit vector variable with offset Actions
Bug #9802: ru.ispras.verilog.parser.sample.FuncTestCase: NullPointerException at ru.ispras.verilog.parser.elaborator.VerilogElaborator.createVariableAndBinding(VerilogElaborator.java:512) Actions
Bug #9803: ru.ispras.verilog.parser.sample.MulFifoTestCase: NullPointerException at ru.ispras.verilog.parser.elaborator.VerilogElaborator$1.getNode(VerilogElaborator.java:932) Actions
Bug #9822: ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_10_04_04_1: Starting points limit has been exhausted: 513 Actions
Bug #9848: ru.ispras.verilog.parser.VerilogVisVerilog2SmvTestCase.runTest_Pci_Bus_Verilog_Mv_files_PciNorm: Function declaration '$ND' has not been found Actions
Bug #9902: java.lang.IllegalArgumentException: Descriptor for '<var name>' has not been found Actions
Bug #9915: "Cycle inclusion has been detected in fine <filename>" error is reported for Verilog modules that use the same another file Actions
Bug #9929: TODO: QuipTestCase extraneous input 'someone' expecting 'someone' Actions
Bug #9936: tabs in "`define" directive cause java.lang.NumberFormatException Actions
Bug #9962: ru.ispras.verilog.parser.sample.Mips16CoreTopTestCase: java.lang.IllegalArgumentException Actions
Bug #9993: if two modules are passed to the tool and one includes another, the tool hangs Actions
Bug #10131: ru.ispras.verilog.parser.VerilogIwlsTestCase.runTest_iscas_s9234_1: java.lang.OutOfMemoryError: Java heap space Actions
Bug #10141: check port redeclarations Actions
Bug #10173: javadoc: DefineStructure.java:37: warning: no @return Actions
Bug #10194: Test test_07_14_02_2_1.v has an error Actions
Bug #10195: Test test_12_04_02_4.v has an error. Actions
Bug #10196: Test mpeg1.v has an error. Actions
Bug #10197: Test const.v has an error. Actions
Bug #10202: SVA grammar warnings via assembling Actions
Bug #10214: ru.ispras.verilog.parser.VerilogQuipTestSuite#runTest_nut_000: nut_000_lut.v line 7:0 no viable alternative at input 'module' Actions
Bug #10215: ERROR: Starting points limit has been exhausted: 2255 Actions
Bug #10216: ru.ispras.verilog.parser.VerilogQuipTestSuite#runTest_nut_001: java.lang.NullPointerException Actions
Bug #10237: ru.ispras.verilog.parser.VerilogTexas97TestSuite#runTest_Pi_Bus_single_master_main2: ERROR: Cycle inclusion at: '...bus.v' Actions
Bug #10241: ru.ispras.verilog.parser.VerilogQuipTestSuite#runTest_dctub_jpeg: ERROR: ..\src\test\verilog\hdl-benchmarks\hdl\quip\oc_video_compression_systems_jpeg\dct_cos_table.v line 1:70 mismatched character '\r' expecting '\n' Actions
Bug #10245: ru.ispras.verilog.parser.VerilogQuipTestSuite#runTest_pci_wbw_wbr_fifos: ERROR: [Internal] null Actions
Bug #10246: ru.ispras.verilog.parser.VerilogQuipTestSuite#runTest_nut_001: ERROR: Module 'lut_output' has not been found Actions
Bug #10382: java.lang.IllegalArgumentException: expression=(BVREPEAT test.uut._saxi_maskwidth 1) Actions
Bug #10502: subbytes.v line 76:13 no viable alternative at input '[' Actions
Bug #10505: ERROR: [Internal] 11 must be within range [0, 1) Actions
Bug #10508: ERROR: [Internal] Java heap space Actions
Bug #10509: ERROR: [Internal] 0 must be > 0 Actions
Bug #10510: ERROR: [Internal] Bit vector sizes do not match: 32 != 2. Actions
Bug #10512: ADDA162H90A_atop.v line 120:47 mismatched input ':' expecting RPAREN Actions
Bug #10513: macOS related line endings at Verilog modules Actions
Feature #8818: Extending grammar to allow else if Actions
Feature #8874: mapping from instance variables to their code entries Actions
Feature #9774: Case expression/value type casting Actions
Feature #9990: check for variable/net redeclarations Actions
Developer Request #5079: Средства обновления переменных модуля Actions
Task #3514: Поддержка в препроцессоре define с параметрами Actions
Task #4097: Проверка зацикливания include-файлов Actions
Task #4126: Unification of AST_EDGE and AST_TABLE_EDGE Actions
Task #4128: Вычисление константных выражений Actions
Task #4392: Add return value for on<Node>(Begin|End) methods Actions
Task #4408: Scope.YES & Scope.NO Actions
Task #4963: Структура данных для представления значений параметров Actions
Task #4964: Типизация переменных Actions
Task #5002: Тип переменной в блоке условия процесса Actions
Task #5010: Conditions in IfStatementBranch Actions
Task #5034: Create a test suite based on the examples of the IEEE 1364-2005 standard Actions
Task #5037: Unification of If(Statement|Generate) и Case(Statement|Generate) Actions
Task #5038: Taking into account X- and Z-don't cares in CaseStatementItem.getExpression(). Actions
Task #5087: Добавить возможность отсечения обхода дочерних поддеревьев Actions
Task #5092: Merging declaration parts for the same variable Actions
Task #5104: Отладка сопоставления ссылок и деклараций Actions
Task #5160: Обработка комментариев в define Actions
Task #5166: Логирования сообщение транслятора Actions
Task #5167: Связывание экземляров модулей с декларациями Actions
Task #5168: Связывание вызовов функций с декларациями Actions
Task #5169: Связывание вызовов задач с декларациями Actions
Task #5174: Добавить в калькулятор поддержку тернарной операции Actions
Task #5205: Подстановка тела функции в место вызова Actions
Task #5206: Обработка конструкций generate Actions
Task #5228: Перенести Expression.VariableGatherer в Fortress Actions
Task #5455: устранить зависимость от ANTLRWorks Actions
Task #5566: Использование стандартного принтера выражений Actions
Task #5651: Translate logic operation results into Boolean expressions Actions
Task #5881: keep file names in the AST top nodes Actions
Task #7524: support for non-zero-starting bit vector variables & signals Actions
Task #7725: bitvector arrays support Actions
Task #8205: Gradle-based build environment Actions
Task #8725: Using Fortress's BitVector in VerilogLiteral Actions
Task #8982: "for" loop unrolling Actions
Task #9206: add Texas97 benchmark to project test suite Actions
Task #9207: add VCEGAR benchmark to project test suite Actions
Task #9208: add Verilog2Smv\VIS benchmark to project test suite Actions
Task #9232: remove typedefs from texas97-tests/PPC60X_bus/src/define.v Actions
Task #9251: calculate type of index for bit-vector arrays Actions
Task #9311: type casting of expression operands Actions
Task #9771: fix 'publishing' block behaviour for Gradle 4.10.3 Actions
Task #9790: external names for unnamed generate blocks Actions
Task #9859: modify "ERROR: [Internal] null" line at error log Actions
Task #9899: VerilogPrinter test cases for QUIP benchmarks Actions
Task #9904: add info for "--library-file" cmdline option Actions
Task #10009: README\ChangeLog -> README.md\ChangeLog.md Actions