Verilog Translator (VeriTrans) is an ANTLR-based Verilog front-end in couple with some back-ends.

Licensing and Distribution

The VeriTrans package is distributed under the Apache License, Version 2.0, which implies the freedom to use the software for any purpose (to distribute it, to modify it and to distribute modified versions of the software) under the terms of the license, but requires preservation of the copyright notice and disclaimer.

The package can be downloaded from the Files page.

Latest news

Verilog Translator 0.1.3 released
Verilog Translator 0.1.3 has been released
Added by Sergey Smolov over 3 years ago

Verilog Translator 0.1.2 released
Verilog Translator 0.1.2 has been released.
Added by Sergey Smolov almost 5 years ago

Verilog Translator 0.1.1 released.
We are happy to announce the first release of the Verilog Translator tool.
Added by Sergey Smolov almost 5 years ago

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