Verilog Translator 0.1.2 released

Added by Sergey Smolov 10 months ago

The release includes the following changes:
  • Type casting for case statement's expression and values;
  • Fix 'publishing' block behaviour in Gradle build system;
  • Bug fixes and general improvements.

The list of resolved issues can be found here

The tool can be downloaded from here

Verilog Translator 0.1.1 released.

Added by Sergey Smolov 12 months ago

Verilog Translator (VeriTrans) is an ANTLR-based Verilog front-end that generates an internal
representation of the target description. The representation is based on an Abstract Syntax Tree
(AST) formalism and on Fortress library objects for expressions representation.

The tool can be downloaded from here


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