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Verilog Translator 0.1.3 released

Added by Sergey Smolov about 2 months ago

The release includes the following changes:

  • Build system: use Gradle 5.0;
  • Documentation: changelog and readme are rewritten into Markdown format;
  • Language: support for macro with parameters;
  • Language: support for SystemVerilog Assertions;
  • Options: `--library-file` option to include function library files;
  • Tests: test cases for QUIP and IWLS'2005 benchmarks;
  • Tool: bug fixes and general improvements;
  • Tool: error diagnostics is improved;
  • Tool: migration to Java 11.

The tool can be downloaded from here
The list of resolved issues can be found here

Verilog Translator 0.1.2 released

Added by Sergey Smolov about 1 year ago

The release includes the following changes:
  • Type casting for case statement's expression and values;
  • Fix 'publishing' block behaviour in Gradle build system;
  • Bug fixes and general improvements.

The list of resolved issues can be found here

The tool can be downloaded from here

Verilog Translator 0.1.1 released.

Added by Sergey Smolov over 1 year ago

Verilog Translator (VeriTrans) is an ANTLR-based Verilog front-end that generates an internal
representation of the target description. The representation is based on an Abstract Syntax Tree
(AST) formalism and on Fortress library objects for expressions representation.

The tool can be downloaded from here

    (1-3/3)

    Also available in: Atom