Sergey Smolov

MicroTESK Documentation (Developer, 12/16/2019)
MicroTESK for PowerPC (Developer, 11/08/2018)
VeriTool (Developer, 04/04/2011)
C++TESK Testing ToolKit (Developer, 07/19/2011)
С++TESK Development Environment (Manager, Developer, 09/07/2011)
Verilog Translator (Manager, Developer, 04/12/2012)
Retrascope (Manager, Developer, Project Creator, 04/12/2012)
MicroTESK (Developer, 08/27/2012)
Fortress (Manager, Developer, 09/19/2012)
Retrascope RISC-V Benchmark (Manager, Developer, Project Creator, 12/19/2018)
MicroTESK Training Course (Developer, 10/03/2013)
TestBase (Developer, 02/25/2014)
Retrascope IDE (Manager, Developer, Project Creator, 05/16/2014)
Java SoftFloat (Reporter, 10/03/2014)
Castle (Manager, Developer, 01/12/2016)
Trace Matcher (Manager, Developer, 11/01/2016)
MicroTESK for RISC-V (Manager, Developer, Project Creator, 11/02/2017)
Retrascope Test Suite (Manager, Developer, Project Creator, 03/28/2018)
QEMU4V (Manager, Project Creator, 05/14/2018)
MicroTESK for MIPS (Developer, 05/17/2018)
Aspectrace (Manager, Developer, 11/14/2019)

01:32 PM Verilog Translator Bug #9822 (Resolved): ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_10_04_04_1: Starting points limit has been exhausted: 513: It is an expected behavior, so the test has been fixed. Sergey Smolov
01:27 PM Verilog Translator Revision 20ccf6e2 (veritrans): fix test; it's an expected behavior (#9822): Signed-off-by: Sergey Smolov <smolov@ispras.ru> Sergey Smolov
01:25 PM Verilog Translator Revision e937b5b9 (veritrans): rename benchmark level test collections: *TestCase -> *TestSuite
Signed-off-by: Sergey Smolov <smolov@ispras.ru> Sergey Smolov

11:54 PM Verilog Translator Bug #10197 (Resolved): Test const.v has an error.: Sergey Smolov
10:05 PM Verilog Translator Bug #10197 (Open): Test const.v has an error.: Sergey Smolov
11:36 PM Verilog Translator Revision e90ffb7b (veritrans): verilog: fix duplicate declaration (#10197): Signed-off-by: Sergey Smolov <smolov@ispras.ru> Sergey Smolov
04:50 PM Retrascope Revision 55753c2c (retrascope): fix javadoc: Signed-off-by: Sergey Smolov <smolov@ispras.ru> Sergey Smolov
03:31 PM Verilog Translator Bug #10202: SVA grammar warnings via assembling: Can this ambiguity be fixed or it comes from the standard? Sergey Smolov
01:37 PM Verilog Translator Revision 185fa2e2 (veritrans): fix CheckStyle warnings: Signed-off-by: Sergey Smolov <smolov@ispras.ru> Sergey Smolov
12:24 PM Verilog Translator Revision c3645f78 (veritrans): rm useless inheritDoc comments: Comments are removed because:
1) there is no need in such comments for
overriding methods;
2) comments for parent... Sergey Smolov

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