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Sergey Smolov

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05/23/2019

01:23 PM Retrascope Revision 8b1a99d0 (retrascope): fixup
Signed-off-by: Sergey Smolov <smolov@ispras.ru> Sergey Smolov
11:35 AM Retrascope Revision 56b05322 (retrascope): debug: reduce b05_part.vhd code to detect bug
To detect which VHDL code produces non-deterministic
extraction of EFSM models, the reduction of "b05_part.vhd"
code ...
Sergey Smolov

05/22/2019

05:00 PM Retrascope MC Benchmark Revision dd936da8: junit: comment Verilog that contain 'assert'
Comment Verilog modules that contain 'assert'
SVA operator. SVA is not supported by Verilog
Translator, it should be ...
Sergey Smolov
03:12 PM Retrascope Revision 95346a84 (retrascope): fix comments
Signed-off-by: Sergey Smolov <smolov@ispras.ru> Sergey Smolov
02:24 PM Retrascope MC Benchmark Task #9670 (New): add 'ar.v' module to the test suite when SVA support will be implemented
See *Ver2SmvBenchmarks* test class. Sergey Smolov
01:40 PM Retrascope MC Benchmark Revision cdab029d: junit: comment 'ar.v' module
Module 'ar.v' contains SystemVerilog Assertions.
Now they're not supported by the Verilog Translator,
so the module i...
Sergey Smolov

05/21/2019

02:38 PM Retrascope MC Benchmark Revision 9e675f5a: junit: update module's include path
Signed-off-by: Sergey Smolov <smolov@ispras.ru> Sergey Smolov
02:22 PM Retrascope MC Benchmark Revision 18093ce3: junit: bugfixes in file paths
Signed-off-by: Sergey Smolov <smolov@ispras.ru> Sergey Smolov

05/17/2019

04:06 PM Retrascope Task #9658 (New): Check for duplicated data access conflict assertions
Sergey Smolov

05/13/2019

06:31 PM Retrascope MC Benchmark Revision 724aecc4: junit: finish IWLS'05 benchmark
Signed-off-by: Sergey Smolov <smolov@ispras.ru> Sergey Smolov

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