Sergey Smolov
Sergey Smolov- Email: smolov@ispras.ru
- Registered on: 03/30/2011
- Last connection: 05/22/2019
Issues
- Assigned issues: 70
- Reported issues: 513
Projects
- VeriTool (Developer, 04/04/2011)
- C++TESK Testing ToolKit (Developer, 07/19/2011)
- ะก++TESK Development Environment (Manager, Developer, 09/07/2011)
- Retrascope (Manager, Developer, Project Creator, 04/12/2012)
- MicroTESK (Developer, 08/27/2012)
- Fortress (Developer, 09/19/2012)
- Retrascope RISC-V Benchmark (Manager, Developer, Project Creator, 12/19/2018)
- MicroTESK Training Course (Developer, 10/03/2013)
- TestBase (Developer, 02/25/2014)
- Retrascope IDE (Manager, Developer, Project Creator, 05/16/2014)
- QEMU for RISC-V (Manager, Developer, Project Creator, 02/01/2019)
- Java SoftFloat (Reporter, 10/03/2014)
- QEMU for ARMv8 (Manager, Developer, Project Creator, 06/19/2015)
- Castle (Manager, Developer, 01/12/2016)
- Trace Matcher (Manager, Developer, 11/01/2016)
- MicroTESK for RISC-V (Manager, Developer, Project Creator, 11/02/2017)
- Retrascope MC Benchmark (Manager, Developer, Project Creator, 03/28/2018)
- QEMU4V (Manager, Project Creator, 05/14/2018)
- MicroTESK for MIPS64 (Developer, 05/17/2018)
Activity
05/23/2019
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01:23 PM Retrascope Revision 8b1a99d0 (retrascope): fixup
- Signed-off-by: Sergey Smolov <smolov@ispras.ru>
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- To detect which VHDL code produces non-deterministic
extraction of EFSM models, the reduction of "b05_part.vhd"
code ...
05/22/2019
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- Comment Verilog modules that contain 'assert'
SVA operator. SVA is not supported by Verilog
Translator, it should be ... -
- Signed-off-by: Sergey Smolov <smolov@ispras.ru>
-
- See *Ver2SmvBenchmarks* test class.
-
- Module 'ar.v' contains SystemVerilog Assertions.
Now they're not supported by the Verilog Translator,
so the module i...
05/21/2019
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- Signed-off-by: Sergey Smolov <smolov@ispras.ru>
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- Signed-off-by: Sergey Smolov <smolov@ispras.ru>
05/17/2019
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05/13/2019
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- Signed-off-by: Sergey Smolov <smolov@ispras.ru>
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