Sergey Smolov
Sergey Smolov- Email: smolov@ispras.ru
- Registered on: 03/30/2011
- Last connection: 12/14/2018
Issues
- Assigned issues: 60
- Reported issues: 484
Projects
- VeriTool (Developer, 04/04/2011)
- C++TESK Testing ToolKit (Developer, 07/19/2011)
- ะก++TESK Development Environment (Manager, Developer, 09/07/2011)
- Retrascope (Manager, Developer, Project Creator, 04/12/2012)
- MicroTESK (Developer, 08/27/2012)
- Fortress (Developer, 09/19/2012)
- MicroTESK Training Course (Developer, 10/03/2013)
- TestBase (Developer, 02/25/2014)
- Retrascope IDE (Manager, Developer, Project Creator, 05/16/2014)
- Java SoftFloat (Reporter, 10/03/2014)
- QEMU for ARMv8 (Manager, Developer, Project Creator, 06/19/2015)
- Castle (Manager, Developer, 01/12/2016)
- Trace Matcher (Manager, Developer, 11/01/2016)
- MicroTESK for RISC-V (Manager, Developer, Project Creator, 11/02/2017)
- QEMU for RISC-V (Manager, Developer, Project Creator, 11/02/2017)
- Retrascope MC Benchmark (Manager, Developer, Project Creator, 03/28/2018)
- QEMU4V (Manager, Project Creator, 05/14/2018)
- MicroTESK for MIPS64 (Developer, 05/17/2018)
Activity
12/13/2018
- 12:16 PM QEMU4V Task #9415 (New): migrate to QEMU 3.1.0
- QEMU 3.1.0 is "out":https://wiki.qemu.org/ChangeLog/3.1. Next release of QEMU4V should be based on it.
12/11/2018
- 02:37 PM QEMU4V Revision 4aeb9056 (qemu4v): ppc: start tracing disasm insn
- Signed-off-by: Sergey Smolov <smolov@ispras.ru>
- 02:22 PM QEMU4V Revision 34958ab1 (qemu4v): ppc: fix insn opcode printing at trace
- Signed-off-by: Sergey Smolov <smolov@ispras.ru>
12/03/2018
- 01:38 PM MicroTESK for RISC-V Revision 21215b26: stub for next version ChangeLog
- Signed-off-by: Sergey Smolov <smolov@ispras.ru>
11/28/2018
- 01:48 PM Retrascope Revision 7955b812 (retrascope): cfg-cgaa:bugifx - put module name, not clock
- Signed-off-by: Sergey Smolov <smolov@ispras.ru>
- 01:33 PM Retrascope Revision edac65c3 (retrascope): cfg-cgaa: iterate on CGAA modules
- Signed-off-by: Sergey Smolov <smolov@ispras.ru>
- 01:27 PM Retrascope MC Benchmark Revision fd4f55ce: verilog: fix implicit typecast in Verilog
- Signed-off-by: Sergey Smolov <smolov@ispras.ru>
11/27/2018
- 06:55 PM Retrascope MC Benchmark Revision dcb8cef9: verilog: non equiv change in VCEGAR module
- Logical AND was substituted to bit-wise.
Signed-off-by: Sergey Smolov <smolov@ispras.ru> - 05:17 PM Retrascope Revision d0bdcd08 (retrascope): cfg-cgaa: specify clock for 'ram' in test
- Signed-off-by: Sergey Smolov <smolov@ispras.ru>
11/26/2018
- 12:20 PM Retrascope Revision a3371229 (retrascope): javadoc header
- Signed-off-by: Sergey Smolov <smolov@ispras.ru>
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