Bug #9190: ru.ispras.verilog.parser.sample.DescriptorBuffersTestCase: incorrect calculation for string parameter values - Verilog Translator - Open-Source Projects

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Bug #9190

closed

ru.ispras.verilog.parser.sample.DescriptorBuffersTestCase: incorrect calculation for string parameter values

Added by Sergey Smolov over 6 years ago. Updated over 6 years ago.

Status:

Closed

Priority:

High

Assignee:

Alexander Kamkin

Target version:

0.1

Start date:

08/03/2018

Due date:

% Done:

Estimated time:

Detected in build:

master

Platform:

Published in build:

Description

The testcase output contains the following description for 'OUTDATA_REG' parameter:

Override parameter: the_write_command_FIFO.the_dp_ram.ram_model.OUTDATA_REG = the_write_command_FIFO.the_dp_ram.outdata_reg_b = Data[type=(BIT_VECTOR 64), value=0010001000110000010010110100001101001111010011000100001100100010]

This parameter is of string type, as it is written in altera_msgdma_mod/dispatcher/altsyncram_model.v:

parameter OUTDATA_REG = "UNREGISTERED"

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Updated by Alexander Kamkin over 6 years ago

The value is correct (not taking the quotes into account):

7: 00100010 22 " 
6: 00110000 30 0
5: 01001011 4B K
4: 01000011 43 C
3: 01001111 4F 0
2: 01001100 4C L
1: 01000011 43 C
0: 00100010 22 "

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Updated by Alexander Kamkin over 6 years ago

Status changed from New to Open

String literal encoding has been fixed:

5: 00110000 30 0
4: 01001011 4B K
3: 01000011 43 C
2: 01001111 4F O
1: 01001100 4C L
0: 01000011 43 C

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Updated by Alexander Kamkin over 6 years ago

A new test case GenerateTestCase has been added. It seems that the problem is in handing generate constructs of nested blocks. The constructs are ignored.

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