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Bug #10336

closed

Incorrect ranges in vhdl/plasma/reg_bank.vhd

Added by Mikhail Lebedev almost 4 years ago. Updated 12 months ago.

Status:
Closed
Priority:
Normal
Assignee:
Sergey Smolov
Category:
Engine (Parser)
Target version:
1.1
Start date:
05/14/2020
Due date:
% Done:

100%

Estimated time:
Detected in build:
git
Platform:
Published in build:
1.1.3-beta-230504

Description

reg_bank design in plasma contains the following array variable:

type ram_type is array(31 downto 0) of std_logic_vector(31 downto 0);
variable tri_port_ram : ram_type;

In CFG model the data type of this variable is correct:
Variable[name=RAM_PROC.TRI_PORT_RAM, data=Data[type=(MAP LOGIC_INTEGER (BIT_VECTOR 32)), value=uninitialized]]

But the variable descriptor contains two ranges for it: 0:31, 0:31
This results in the following incorrect SMV-code:

VAR
  RAM_PROC_TRI_PORT_RAM : array 0..31 of array 0..31 of word[32];

One range is excessive.

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 #1

Updated by Sergey Smolov almost 4 years ago

  • Category set to Engine (Parser)
  • Status changed from New to Resolved
  • Target version set to 1.1
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 #2

Updated by Mikhail Lebedev almost 4 years ago

  • Status changed from Resolved to Verified
  • % Done changed from 0 to 100
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 #3

Updated by Sergey Smolov almost 4 years ago

  • Subject changed from Incorrect ranges in vhdl/plasma/reg_bank.vhdl to Incorrect ranges in vhdl/plasma/reg_bank.vhd
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 #4

Updated by Sergey Smolov 12 months ago

  • Status changed from Verified to Closed
  • Published in build set to 1.1.3-beta-230504
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