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Overview

Retrascope is a toolkit for Reverse Engineering, visualization and TRAnsformation of digital hardware designs described in such HDLs (hardware description languages) as Verilog and VHDL. The toolkit allows analyzing HDL descriptions, reconstructing and visualization of the underlying models (extended finite state machines, EFSMs) and using the derived models for test generation, property checking and other tasks. Retrascope is organized as an extendible framework with the ability to add new types of models as well as tools for their analysis and transformation. The primary application domain of the toolkit is functional verification of hardware at the unit level.

More info is available in Wiki

Contacts

Office 25 Alexander Solzhenitsyn st., rooms 210 and 211, Moscow, 109004, Russia
E-mail retrascope-support [at] ispras.ru

Licensing and Distribution

The Retrascope package is distributed under the Apache License, Version 2.0, which implies the freedom to use the software for any purpose (to distribute it, to modify it and to distribute modified versions of the software) under the terms of the license, but requires preservation of the copyright notice and disclaimer.

The package can be downloaded from the Files page.

Project dependencies

Project License Description
ANTLR3 BSD License Parsing Verilog files
Castle Apache License, 2.0 Developing translators and code generators
Commons CLI Apache License, 2.0 Parsing command line options
Commons Collections Apache License, 2.0 Manipulating with bidirectional mappings
Commons IO Apache License, 2.0 Processing for inputs\outputs
Commons Lang Apache License, 2.0 Providing utility methods
Commons Logging Apache License, 2.0 Providing logging utilities
Fortress Apache License, 2.0 Representing expressions and solving constraints
Jython Python Software Foundation License Version 2 Supporting zamiaCAD operation
JUNG BSD License Operating with graphs
JUnit Eclipse Public License 1.0 Testing project classes
Log4J Apache License, 2.0 Operating with logging options of zamiaCAD
Log5J Apache License, 2.0 Operating with Log4j library
Verilog Translator Apache License, 2.0 Building AST from Verilog files
zamiaCAD GNU General Public License Version 3 Processing VHDL files

Latest news

Retrascope 1.0.1 released
Retrascope 1.0.1 (formerly HDL Retrascope) has been released.
Added by Sergey Smolov over 1 year ago

HDL Retrascope 0.2.2 released
HDL Retrascope 0.2.2 has been released.
Added by Sergey Smolov about 2 years ago

HDL Retrascope was presented at DATE 2016
Added by Sergey Smolov over 2 years ago

HDL Retrascope 0.2.1 released
HDL Retrascope 0.2.1 has been released.
Added by Sergey Smolov almost 3 years ago

HDL Retrascope 0.1.3 released
HDL Retrascope 0.1.3 has been released.
Added by Sergey Smolov over 3 years ago

View all news