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1.1

open

77%

31 issues   (4 closed — 27 open)

Related issues
Bug #10023: ru.ispras.retrascope.parser.verilog.VerilogParserTestCase: java.lang.Exception: Method runTest should have no parameters Actions
Bug #10075: jython.jar: WARNING: An illegal reflective access operation has occurred at JDK 11 Actions
Bug #10081: tool hangs right after final "Duration: " msg Actions
Bug #10082: WARNING: Illegal reflective access by org.python.core.PySystemState Actions
Bug #10085: EfsmTransitionPropertyExtractorTestCase: There is no declaration of variable neither in this EFSM nor in its ancestors: process_0.D Actions
Bug #10097: no such method exception: ParameterResolver in all TestCases Actions
Bug #10104: Wiki documentation errata Actions
Bug #10174: nondeterminism at EFSM transitions generation Actions
Bug #10191: java.lang.IllegalArgumentException: Specified target vertex 0 is not part of graph Actions
Bug #10236: efsm-test-generator hangs at opencores/mips16/data_mem.v Actions
Bug #10266: ru.ispras.retrascope.engine.hldd.printer.smv.HlddSmvPrinterTestCase.runTest: java.lang.NullPointerException Actions
Bug #10289: ru.ispras.retrascope.engine.hldd.printer.smv.property.HlddPropertySmvPrinterTestCase.runTest: java.lang.OutOfMemoryError: Java heap space Actions
Bug #10336: Incorrect ranges in vhdl/plasma/reg_bank.vhd Actions
Bug #10462: Разработка VCD printer. Тип переменной "NULL" Actions
Feature #10112: '--no-phase' command line option for 'cfg-gadd-transformer' engine Actions
Feature #10115: '--version' command line option Actions
Feature #10116: command line option to check if solvers\model checkers that are used are installed properly Actions
Feature #10125: '--detailed' option for efsm-graphml-printer engine Actions
Feature #10238: VerilogParser: '--library-file' cmdline option Actions
Feature #10287: TestModel: keep top level module name & variables Actions
Task #4877: Разработка конвертера тестовой последовательности в VCD-формат Actions
Task #9911: merge "*/sample/*TestCase" Java test cases Actions
Task #9964: add HDL examples to project distribution Actions
Task #10000: README\ChangeLog -> README.md\ChangeLog.md Actions
Task #10059: mv all the project tests to JUnit 5 platform Actions
Task #10073: fix checkstyle warnings Actions
Task #10128: rename multi-test classes: "*TestCase" -> "*TestSuite" Actions
Task #10133: use '-coi' model checker option Actions
Task #10139: fix coding issues at *BenchTest classes Actions
Task #10166: rename some class fields & related methods Actions
Task #10230: Java version in README.md Actions

1.2

open

SVA support, simple CFG-to-C printer, documentation

16%

6 issues   (0 closed — 6 open)

Related issues
Feature #9247: CFG-to-C printer Actions
Feature #10060: Support SVA properties in CFG model Actions
Task #5150: Обработка функций - реализация макроподстановок Actions
Task #5504: add channels between EFSMs Actions
Task #9488: CFG-GADD transformer backend that makes assignments index and range-free Actions
Task #10058: User documentation Actions

2.0

open

Features: flowchart extraction and visualization, RTL-to-TLM abstraction, testbench generation (UVM and C++TESK), property and protocol specification, deadlock analysis

0%

17 issues   (0 closed — 17 open)

Related issues
Feature #4057: Механизм поиска взаимных блокировок Actions
Task #4363: Критерий кластеризации входных сигналов, основанный на GA Actions
Task #4521: Входной класс для генератора тестовой последовательности Actions
Task #4880: Проектирование внутреннего представления для блок-схем Actions
Task #4881: Реализация алгоритма построения блок-схем по внутреннему представлению Actions
Task #4882: Разработка принтеров блок-схем в графические форматы Actions
Task #4887: Разработка внутреннего представления тестовой системы Actions
Task #4888: Генератор заготовки тестовой системы по ее описанию Actions
Task #4889: Генерация заготовки эталонной модели по набору блок-схем (flowchart) Actions
Task #4890: Разработка и реализация метода RTL-в-TLM абстракции блок-схем Actions
Task #4891: Реализация генератора тестов по набору блок-схем Actions
Task #4892: Анализ набора блок-схем на взаимные блокировки Actions
Task #4962: Реализация утилиты Veritool с помощью средств Retrascope Actions
Task #5027: Абстракция EFSM-моделей Actions
Task #6446: Promela translator to CFG representation (no buffers) Actions
Task #6448: mapping description language + IR + parser Actions
Task #6449: testbench generator taking test sequences and mappings as inputs Actions