Mikhail Lebedev - Open-Source Projects

Mikhail Lebedev

Email: lebedev@ispras.ru
Registered on: 10/10/2012
Last connection: 06/10/2019

Issues

Assigned issues: 7
Reported issues: 42

Projects

Retrascope (Developer, 10/10/2012)
Fortress (Developer, 12/05/2012)
Retrascope RISC-V Benchmark (Developer, 12/19/2018)
Retrascope IDE (Developer, 05/16/2014)
Verilog Translator (Developer, 02/25/2015)
MicroTESK (Developer, 10/16/2017)
Retrascope Test Suite (Developer, 03/28/2018)
QEMU4V (Developer, 05/15/2018)

Activity

10/11/2019

06:05 PM Verilog Translator Revision c8570442 (veritrans): SVA grammar refactoring & debug:: - property & sequence AST modified
- some lexer tokens removed, pp added
- some unsupported SV features removed from ... Mikhail Lebedev

10/10/2019

06:46 PM Verilog Translator Revision cbfb6c24 (veritrans): some bugs in SVA grammar fixed: Signed-off-by: Mikhail Lebedev <lebedev@ispras.ru> Mikhail Lebedev
03:06 PM Verilog Translator Revision 253c9b02 (veritrans): SVA debug: Signed-off-by: Mikhail Lebedev <lebedev@ispras.ru> Mikhail Lebedev

10/08/2019

06:27 PM Verilog Translator Revision 00d741ba (veritrans): new SVA test cases added: Signed-off-by: Mikhail Lebedev <lebedev@ispras.ru> Mikhail Lebedev
06:14 PM Verilog Translator Revision aae0ed11 (veritrans): SVA references support improved: Signed-off-by: Mikhail Lebedev <lebedev@ispras.ru> Mikhail Lebedev

10/04/2019

05:07 PM Verilog Translator Revision 8bb1331b (veritrans): - SVA grammar code style improved: - SVA expressions unified & inherited from VerilogExpression
- some classes simplified or deleted
Signed-off-by: Mik... Mikhail Lebedev

10/03/2019

03:38 PM Verilog Translator Revision b08e0b62 (veritrans): SVA grammar refactoring:: - some grammar simplification
- sequence & property instances replaced by reference
- compile- and runtime 'code too ... Mikhail Lebedev

10/01/2019

05:37 PM Verilog Translator Revision 747d93d4 (veritrans): some SVA parser grammar improvements: Signed-off-by: Mikhail Lebedev <lebedev@ispras.ru> Mikhail Lebedev
02:38 PM Verilog Translator Revision f9ce303b (veritrans): further SVA debug: Signed-off-by: Mikhail Lebedev <lebedev@ispras.ru> Mikhail Lebedev

09/20/2019

04:38 PM Verilog Translator Revision bd24f0cc (veritrans): SVA grammar debug; test cases added: Signed-off-by: Mikhail Lebedev <lebedev@ispras.ru> Mikhail Lebedev

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