Mikhail Lebedev - Open-Source Projects

Mikhail Lebedev

Email: lebedev@ispras.ru
Registered on: 10/10/2012
Last connection: 12/19/2019

Issues

Assigned issues: 8
Reported issues: 42

Projects

MicroTESK Documentation (Developer, 12/16/2019)
Retrascope (Developer, 10/10/2012)
Fortress (Developer, 12/05/2012)
Retrascope RISC-V Benchmark (Developer, 12/19/2018)
Retrascope IDE (Developer, 05/16/2014)
Verilog Translator (Developer, 02/25/2015)
MicroTESK (Developer, 10/16/2017)
Retrascope Test Suite (Developer, 03/28/2018)
QEMU4V (Developer, 05/15/2018)

Activity

01/13/2020

04:25 PM Verilog Translator Revision f56336fc (veritrans): Added a couple of assertion tests to Vcegar.: Signed-off-by: Mikhail Lebedev <lebedev@ispras.ru> Mikhail Lebedev
04:02 PM Verilog Translator Revision 428d729d (veritrans): Grammar ambiguity between sva & verilog expressions fixed;: Verilog2Smv tests uncommented;
Signed-off-by: Mikhail Lebedev <lebedev@ispras.ru> Mikhail Lebedev

12/24/2019

06:58 PM Verilog Translator Revision bfa70983 (veritrans): Merge branch 'master' of https://forge.ispras.ru/git/veritrans: Mikhail Lebedev
06:57 PM Verilog Translator Revision 5036f240 (veritrans): Debug after merge: Signed-off-by: Mikhail Lebedev <lebedev@ispras.ru> Mikhail Lebedev
03:36 PM Verilog Translator Revision 3b92139e (veritrans): Merge branch 'sva.grammar': Mikhail Lebedev

12/23/2019

07:28 PM Verilog Translator Revision 4f096401 (veritrans): - added sequence/property declaration representation in the elaborated: design
- improved sequence/property instance recognition by adding a syntax backend
Signed-off-by: Mikhail Lebedev <... Mikhail Lebedev

12/19/2019

05:59 PM Verilog Translator Revision 295f1067 (veritrans): Improved sequence/property support in tree builder, added instance: operations to sva operations.
Signed-off-by: Mikhail Lebedev <lebedev@ispras.ru> Mikhail Lebedev

12/18/2019

04:32 PM Verilog Translator Revision fc41e450 (veritrans): assertion statements elaboration added, deferred assertions grammar: debug.
Signed-off-by: Mikhail Lebedev <lebedev@ispras.ru> Mikhail Lebedev
02:08 PM Verilog Translator Revision 37efec09 (veritrans): SVA checks added to static checker, some new tests added, debug.: Signed-off-by: Mikhail Lebedev <lebedev@ispras.ru> Mikhail Lebedev

12/03/2019

05:30 PM Verilog Translator Revision d316d172 (veritrans): Some SV system tasks & functions added to VerilogLibrary: Signed-off-by: Mikhail Lebedev <lebedev@ispras.ru> Mikhail Lebedev

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