Open-Source Projects

11/08/2019

04:49 PM Verilog Translator Revision 849549a9 (veritrans): Branch merge

Signed-off-by: Mikhail Lebedev <lebedev@ispras.ru> Mikhail Lebedev

04:34 PM Verilog Translator Revision a8375bb7 (veritrans): Rebased master, adapted ieee verilog tests to sva grammar (found 'int',

'byte' sv keywords), some grammar debug
Signed-off-by: Mikhail Lebedev <lebedev@ispras.ru> Mikhail Lebedev

02:44 PM Verilog Translator Revision 050ebe92 (veritrans): - elaboration of SVA constructs added;

- copy constructors in sva expressions fixed;
- printing of some SVA constructs added to VerilogNodePrinter;
- small ... Mikhail Lebedev

02:44 PM Verilog Translator Revision 72b919e3 (veritrans): SVA ports: some grammar debug, declarations added, empty types in

declarations permitted.
Signed-off-by: Mikhail Lebedev <lebedev@ispras.ru> Mikhail Lebedev

02:44 PM Verilog Translator Revision ebe0e96b (veritrans): SVA printing debug

Signed-off-by: Mikhail Lebedev <lebedev@ispras.ru> Mikhail Lebedev

02:44 PM Verilog Translator Revision 83820a0e (veritrans): SVA bug fixes

Signed-off-by: Mikhail Lebedev <lebedev@ispras.ru> Mikhail Lebedev

02:44 PM Verilog Translator Revision c45e128b (veritrans): SVA grammar refactoring:

- property & sequence expressions merged into sva_expr
- some other grammar changes
- all sva-ieee tests pass
Signed... Mikhail Lebedev

02:44 PM Verilog Translator Revision 0e64cd1d (veritrans): Fortress node construction added to SVA grammar, AST classes refactoring

Signed-off-by: Mikhail Lebedev <lebedev@ispras.ru> Mikhail Lebedev

02:44 PM Verilog Translator Revision 20b2d2cc (veritrans): - SVA sequence & property packages -> expression package, classes

renamed;
- some other refactoring;
Signed-off-by: Mikhail Lebedev <lebedev@ispras.ru> Mikhail Lebedev

02:44 PM Verilog Translator Revision 0589c0e2 (veritrans): comments added to SVA classes

Signed-off-by: Mikhail Lebedev <lebedev@ispras.ru> Mikhail Lebedev