Actions
Bug #10336
closedIncorrect ranges in vhdl/plasma/reg_bank.vhd
Start date:
05/14/2020
Due date:
% Done:
100%
Estimated time:
Detected in build:
git
Platform:
Published in build:
1.1.3-beta-230504
Description
reg_bank
design in plasma contains the following array variable:
type ram_type is array(31 downto 0) of std_logic_vector(31 downto 0); variable tri_port_ram : ram_type;
In CFG model the data type of this variable is correct:
Variable[name=RAM_PROC.TRI_PORT_RAM, data=Data[type=(MAP LOGIC_INTEGER (BIT_VECTOR 32)), value=uninitialized]]
But the variable descriptor contains two ranges for it: 0:31, 0:31
This results in the following incorrect SMV-code:
VAR RAM_PROC_TRI_PORT_RAM : array 0..31 of array 0..31 of word[32];
One range is excessive.
Actions