Command Line Options¶

• Table of contents
• Command Line Options
  • Source files
  • Targets
  • Engines
  • Logging

One way to use the HDL Retrascope is it''s command line options. Here is an output of the tool that it run with "--help" option:

usage: [options] files
 -e,--engine <arg>   Set a subset of engines
 -h,--help           Show this message
 -l,--log <arg>      Set a log file
 -t,--target <arg>   Set a target entity

This output shows four main categories of HDL Retrascope command line options: source files, engines, logging mode and targets.
Options can be put into command line in an arbitrary order.

Source files¶

This option keeps paths to files that contain source code of hardware modules.

The HDL Retrascope can elaborate hardware descriptions written in synthesizable subsets of VHDL and Verilog. For current version of the tool it is possible to elaborate the source code when it satisfies some limitations.

For VHDL - no loop-cycles, no other modules'' instantiations, no wait-constructions, no function calls, no ''Z'' or ''X'' values, code size is less than 1 KLOC.
For Verilog - similar to VHDL.

If these limitations are satisfied there is a high probability that HDL Retrascope will be able to elaborate your design:-) Otherwise an exception will occur.
It is possible to run the HDL Retrascope both on several VHDL and Verilog designs. In such case a composite inner representation based on Control FLow Graph model will be constructed.

To transform Verilog design into Control Flow Graph model you need to run HDL Retrascope with the following parameters:

--target cfg /path/to/file/file.v

where "cfg" encodes Controlf Flow Graph model as target.

To transform VHDL design into Control Flow Graph model you need to run HDL Retrascope with the following parameters:

--target cfg --toplevel toplevel_name /path/to/file/file.vhd

where "toplevel" is an option that is obligatory for all VHDL designs that are being elaborated. The toplevel option value is a string name of the top-level module of the specified VHDL file. For example, to elaborate the following VHDL design (that is saved in the hello.vhd file):

entity hello_world is
end;

architecture hello_world_arc of hello_world is
begin
  stimulus : process
  begin
    assert false report "Hello World" 
    severity note;
  end process stimulus;
end hello_world_arc;

we need to run HDL Retrascope with the following parameters:

--target cfg --toplevel hello_world /path/to/file/hello.vhd

Targets¶

From the tool point of view, the HDL Retrascope operates with entities. One kind of these entities called "source files" was described in the previous section and for it''s elaboration the default tool components (called HDL parsers) are used.

Other entities may be treated as equivalent transformations of source code, or as data that can be extracted from source code (for example, like knowledge about module interfaces) or constructed (like module-level tests). Every entity which representation is included into HDL Retrascope is stronlge connected with the tool component called "engine".

To select the entity the user wants to get as result, the "target" option is needed to be initialized. For example, to get the EFSM (Extended Finite State Machine) that is stored into GraphML graphical format (see http://graphml.graphdrawing.org/), the HDL Retrascope should be run with the following options (for Verilog design called example.v):

--target efsm-graphml example.v

Engines¶

Logging¶