Retrascope is a toolkit for Reverse Engineering and TRAnsformation of digital hardware designs described in such HDLs (hardware description languages) as Verilog and VHDL. The toolkit allows analyzing HDL descriptions, reconstructing the underlying models (extended finite state machines, EFSMs) and using the derived models for test generation, property checking and other tasks. Retrascope is organized as an extendible framework with the ability to add new types of models as well as tools for their analysis and transformation. The primary application domain of the toolkit is functional verification of hardware at the unit level.

Licensing and Distribution

The Retrascope package is distributed under the Apache License, Version 2.0, which implies the freedom to use the software for any purpose (to distribute it, to modify it and to distribute modified versions of the software) under the terms of the license, but requires preservation of the copyright notice and disclaimer.

The package can be downloaded from the Files page.

E-mail: retrascope-support [at] ispras.ru

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Latest news

HDL Retrascope 0.2.2 released
HDL Retrascope 0.2.2 has been released.
Added by Sergey Smolov 4 months ago

HDL Retrascope was presented at DATE 2016
Added by Sergey Smolov 11 months ago

HDL Retrascope 0.2.1 released
HDL Retrascope 0.2.1 has been released.
Added by Sergey Smolov 12 months ago

HDL Retrascope 0.1.3 released
HDL Retrascope 0.1.3 has been released.
Added by Sergey Smolov over 1 year ago

HDL Retrascope was presented at DATE 2015
The HDL Retrascope toolkit was presented at the University Booth of the DATE 2015 conference on March 9-13 in Grenoble, France.
Added by Sergey Smolov almost 2 years ago

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