Project

General

Profile

Command Line Options » History » Version 17

Sergey Smolov, 12/24/2014 06:17 PM

1 1 Sergey Smolov
h1. Command Line Options
2
3 2 Sergey Smolov
{{toc}}
4
5 17 Sergey Smolov
One way to use the "HDL Retrascope":http://forge.ispras.ru/projects/retrascope is it''s command line options. Here is an output of the tool that is run with "--help" option:
6 1 Sergey Smolov
7
<pre>
8
usage: [options] files
9 9 Sergey Smolov
 --engine <arg>   Set a subset of engines
10
 --help           Show this message
11
 --log <arg>      Set a log file
12
 --target <arg>   Set a target entity
13 1 Sergey Smolov
</pre>
14
15
This output shows four main categories of "HDL Retrascope":http://forge.ispras.ru/projects/retrascope command line options: source files, engines, logging mode and targets.
16
Options can be put into command line in an arbitrary order. 
17
18 16 Sergey Smolov
Options can have multi-values i.e. sequences of values, separated by system-dependent symbols. For example, for running the tool on multiple Verilog files (@file1.v@, @file2.v@, @file3.v@) on *nix OS, do the following:
19
20
<pre>
21
--target cfg file1.v:file2.v:file3.v
22
</pre>
23
24
while on Windows:
25
26
<pre>
27
--target cfg file1.v;file2.v;file3.v
28
</pre>
29
30
31 1 Sergey Smolov
h2. Source files
32
33
This option keeps paths to files that contain source code of hardware modules.
34
35
The "HDL Retrascope":http://forge.ispras.ru/projects/retrascope can elaborate hardware descriptions written in synthesizable subsets of VHDL and Verilog. For current version of the tool it is possible to elaborate the source code when it satisfies some limitations. 
36
37
For VHDL - no loop-cycles, no other modules'' instantiations, no wait-constructions, no function calls, no ''Z'' or ''X'' values, code size is less than 1 KLOC.
38
For Verilog - similar to VHDL.
39
40
If these limitations are satisfied there is a high probability that "HDL Retrascope":http://forge.ispras.ru/projects/retrascope will be able to elaborate your design:-) Otherwise an exception will occur.
41
It is possible to run the "HDL Retrascope":http://forge.ispras.ru/projects/retrascope both on several VHDL and Verilog designs. In such case a composite inner representation based on Control FLow Graph model will be constructed.
42
43
To transform Verilog design into Control Flow Graph model you need to run "HDL Retrascope":http://forge.ispras.ru/projects/retrascope with the following parameters:
44
45
<pre>
46
--target cfg /path/to/file/file.v
47
</pre>
48
49
where "cfg" encodes Controlf Flow Graph model as target.
50
51
To transform VHDL design into Control Flow Graph model you need to run "HDL Retrascope":http://forge.ispras.ru/projects/retrascope with the following parameters:
52
53
<pre>
54
--target cfg --toplevel toplevel_name /path/to/file/file.vhd
55
</pre>
56
57 3 Sergey Smolov
where "toplevel" is an option that is obligatory for all VHDL designs that are being elaborated. The toplevel option value is a string name of the top-level module of the specified VHDL file. For example, to elaborate the following VHDL design (that is saved in the hello.vhd file):
58
59
<pre>
60
entity hello_world is
61
end;
62
 
63
architecture hello_world_arc of hello_world is
64
begin
65
  stimulus : process
66
  begin
67 4 Sergey Smolov
    assert false report "Hello World"
68 3 Sergey Smolov
    severity note;
69
  end process stimulus;
70
end hello_world_arc;
71
</pre>
72
73
we need to run "HDL Retrascope":http://forge.ispras.ru/projects/retrascope with the following parameters:
74
75
<pre>
76
--target cfg --toplevel hello_world /path/to/file/hello.vhd
77
</pre>
78 2 Sergey Smolov
79
h2. Targets
80
81 5 Sergey Smolov
From the tool point of view, the "HDL Retrascope":http://forge.ispras.ru/projects/retrascope operates with entities. One kind of these entities called "source files" was described in the previous section and for it''s elaboration the default tool components (called HDL parsers) are used.
82
83
Other entities may be treated as equivalent transformations of source code, or as data that can be extracted from source code (for example, like knowledge about module interfaces) or constructed (like module-level tests). Every entity which representation is included into "HDL Retrascope":http://forge.ispras.ru/projects/retrascope is stronlge connected with the tool component called "engine".
84
85 7 Sergey Smolov
To select the entity the user wants to get as result, the "target" option is needed to be initialized. For example, to get the EFSM (Extended Finite State Machine) that is stored into "GraphML":http://graphml.graphdrawing.org graphical format, the "HDL Retrascope":http://forge.ispras.ru/projects/retrascope should be run with the following options (for Verilog design called example.v):
86 5 Sergey Smolov
87
<pre>
88
--target efsm-graphml example.v
89
</pre>
90
91 8 Sergey Smolov
Here is the list of all target options of "HDL Retrascope":http://forge.ispras.ru/projects/retrascope:
92 6 Sergey Smolov
|*Name*|*Description*|
93
|cfg|Control flow graph model|
94 8 Sergey Smolov
|cfg-graphml|Control flow graph model that is saved in the "GraphML":http://graphml.graphdrawing.org file|
95 6 Sergey Smolov
|cfginterface|Interface (input and output signals) of control flow graph model|
96
|cgaa|Clocked guarded atomic actions model|
97 8 Sergey Smolov
|cgaa-graphml|Clocked guarded atomic actions model that is saved in the "GraphML":http://graphml.graphdrawing.org file|
98 6 Sergey Smolov
|efsm|Extended finite state machine model|
99 8 Sergey Smolov
|efsm-graphml|Extended finite state machine model that is saved in the "GraphML":http://graphml.graphdrawing.org file|
100 1 Sergey Smolov
101
h2. Engines
102
103 8 Sergey Smolov
As it is described above, the "HDL Retrascope":http://forge.ispras.ru/projects/retrascope consists of components called "engines" for source files & models elaboration. The "HDL Retrascope":http://forge.ispras.ru/projects/retrascope tool takes the target and constructs a sequence of engines called "toolchain" that reaches the specified target as a result. If the specified target is unreachable, the tool returns an error message.
104
When the specified target can be reached by several toolchains, the user can select the desired one by selecting engines with special option called "engine".
105
Here is the list of all engines of "HDL Retrascope":http://forge.ispras.ru/projects/retrascope:
106
|*Name*|*Description*|
107
|verilog-parser|Parser of hardware modules descriptions written in Verilog|
108
|vhdl-parser|Parser of hardware modules descriptions written in VHDL|
109
|cfg-graphml-printer|Printer of control flow graph model into "GraphML":http://graphml.graphdrawing.org format|
110
|cfg-cgaa-transformer|Transformer of control flow graph model into clocked guarded actions model|
111
|cfg-cfginterface-extractor|Extractor of interface signals of control flow graph model|
112
|cgaa-graphml-printer|Printer of clocked guarded atomic actions model into "GraphML":http://graphml.graphdrawing.org format|
113
|cgaa-efsm-transformer|Transformer of control flow graph model into extended finite state machine model|
114
|efsm-graphml-printer|Printer of extended finite state machine model into "GraphML":http://graphml.graphdrawing.org format|
115
|efsm-fate-test-generator|The "FATE":http://link.springer.com/article/10.1007%2Fs10836-011-5209-8 test generator from extended finite state machine model|
116 1 Sergey Smolov
|efsm-test-generator| Generator of tests from extended finite state machine model|
117
|test-xml-printer|Printer of tests into XML format|
118
|xml-test-parser|Parser of XML format files keeping the tests|
119 8 Sergey Smolov
120 14 Sergey Smolov
Some options are common for all the tool engines. Here they are:
121
|*Option name*|*Description*|*Acceptable value*|
122
|printer-style|Set a printer style|VERILOG/VHDL|
123 11 Sergey Smolov
124 14 Sergey Smolov
Some engines have individual command line options. Here is the list of all engine-specific options:
125
126 15 Sergey Smolov
|*Engine name*|*Option*|*Description*|*Acceptable value*|*Default value*|
127
|verilog-parser|include-path|Path to find included files|Any existing file system path|empty|
128
|vhdl-parser|toplevel|Toplevel VHDL modules names|Name of toplevel module for the processed VHDL module(s)|empty|
129
|cfg-graphml-printer|cfg-graphml|Output GraphML file name|Any string name for file that is acceptable by OS|cfg-model.graphml|
130
|cgaa-graphml-printer|cgaa-graphml|Output GraphML file name|Any string name for file that is acceptable by OS|cgaa-model.graphml|
131
|efsm-graphml-printer|efsm-graphml|Output GraphML file name|Any string name for file that is acceptable by OS|efsm-model.graphml|
132
|efsm-fate-test-generator|sequence-length|Amount of vectors in one randomly generated sequence|??|??|
133
|efsm-fate-test-generator|sequences-number|Amount of sequences in a randomly generated fragment of a test|??|??|
134
|efsm-test-generator|loop-limit|Loop iteration limit|??|??|
135
|test-xml-printer|file-name|Output XML file name|Any string name for file that is acceptable by OS|test.xml|
136 2 Sergey Smolov
137
h2. Logging
138 10 Sergey Smolov
139
By default, "HDL Retrascope":http://forge.ispras.ru/projects/retrascope prints it''s output to the standard error stream. It is also possible to redirect the tool output to the specified by using <code>--log</code> option.