RISC-V Instruction Set » History » Version 46
Andrei Tatarnikov, 07/26/2018 06:01 PM
1 | 7 | Andrei Tatarnikov | h1. Instructions supported by MicroTESK for RISC-V |
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3 | 41 | Andrei Tatarnikov | The table below shows the status of support for particular instructions in MicroTESK for RISC-V. |
4 | 38 | Andrei Tatarnikov | |
5 | 42 | Andrei Tatarnikov | Here is the explanation of the meaning of the <code>Specified</code> and <code>Validated</code> columns: |
6 | 38 | Andrei Tatarnikov | |
7 | 45 | Andrei Tatarnikov | To be supported in MicroTESK, instructions need to be described in formal specifications. The <code>Specified</code> column shows whether specific instructions have been described in the specifications. |
8 | 1 | Alexander Protsenko | |
9 | 46 | Andrei Tatarnikov | The instruction semantics described in specifications may be incomplete or invalid. Therefore, instruction specifications must be validated with tests (e.g. ones ported from https://github.com/riscv/riscv-tests). To perform validation, the tests are executed in an ISA simulator constructed on the basis of the specifications. The <code>Validated</code> column shows whether the specifications of specific instructions have been validated with tests. |
10 | 1 | Alexander Protsenko | |
11 | 42 | Andrei Tatarnikov | NOTE: Incomplete or invalid semantics of instruction in specifications does not that these instructions cannot be used in test programs. It just prevents using them in tests that require information on the current state of registers and memory (e.g. self-checking tests and constraint-based tests). In general, to generate random tests, only the syntax of instructions is required to be valid while the semantics may be incomplete. |
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13 | There are three statuses of support based on the two columns and marked with colors: |
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14 | |||
15 | {background:#cfc}. | Fully supported (fully specified and validated) | |
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16 | {background:#ff9}. | Partially supported (specified, but not fully validated) | |
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17 | {background:#fcc}. | Currently unsupported (not specified and not validated yet) | |
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18 | 39 | Andrei Tatarnikov | |
19 | 44 | Andrei Tatarnikov | h2. Instruction table |
20 | 43 | Andrei Tatarnikov | |
21 | 11 | Andrei Tatarnikov | {font-weight:bold; background:#ddd}. | Instruction Set | Instructions | Specified | Validated | |
22 | 30 | Andrei Tatarnikov | {background:#cfc}. | *RV32I (User)* | LUI |
23 | 19 | Andrei Tatarnikov | AUIPC |
24 | JAL |
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25 | JALR |
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26 | BEQ |
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27 | BNE |
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28 | BLT |
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29 | BGE |
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30 | BLTU |
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31 | BGEU |
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32 | LB |
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33 | LH |
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34 | LW |
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35 | LBU |
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36 | LHU |
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37 | SB |
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38 | SH |
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39 | SW |
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40 | ADDI |
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41 | SLTI |
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42 | SLTIU |
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43 | XORI |
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44 | ORI |
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45 | ANDI |
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46 | SLLI |
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47 | SRLI |
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48 | SRAI |
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49 | SLL |
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50 | SRL |
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51 | SRA |
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52 | ADD |
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53 | SUB |
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54 | SLT |
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55 | SLTU |
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56 | XOR |
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57 | OR |
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58 | 23 | Andrei Tatarnikov | AND | Yes (37/37) | Yes (37/37) | |
59 | 30 | Andrei Tatarnikov | {background:#cfc}. | *RV64I (User)* | LWU |
60 | 22 | Andrei Tatarnikov | LD |
61 | SD |
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62 | ADDIW |
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63 | SLLIW |
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64 | SRLIW |
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65 | SRAIW |
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66 | ADDW |
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67 | SUBW |
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68 | SLLW |
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69 | 1 | Alexander Protsenko | SRLW |
70 | SRAW | Yes (12/12) | Yes (12/12) | |
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71 | 30 | Andrei Tatarnikov | {background:#ff9}. | *RV32I (System)* | ECALL |
72 | EBREAK |
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73 | FENCE |
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74 | FENCE.I |
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75 | MRET |
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76 | SRET |
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77 | URET |
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78 | WFI |
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79 | CSRRW |
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80 | CSRRS |
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81 | CSRRC |
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82 | CSRRWI |
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83 | CSRRSI |
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84 | 31 | Andrei Tatarnikov | CSRRCI | Yes (14/14) | No (0/14) | |
85 | 15 | Andrei Tatarnikov | {background:#cfc}. | *RV32M* | MUL |
86 | 18 | Andrei Tatarnikov | MULH |
87 | MULHSU |
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88 | MULHU |
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89 | DIV |
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90 | DIVU |
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91 | REM |
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92 | REMU | Yes (8/8) | Yes (8/8) | |
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93 | 15 | Andrei Tatarnikov | {background:#cfc}. | *RV64M* | MULW |
94 | 18 | Andrei Tatarnikov | DIVW |
95 | DIVUW |
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96 | REMW |
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97 | REMUW | Yes (5/5) | Yes (5/5) | |
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98 | 15 | Andrei Tatarnikov | {background:#cfc}. | *RV32A* | LR.W |
99 | 18 | Andrei Tatarnikov | SC.W |
100 | AMOSWAP.W |
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101 | AMOADD.W |
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102 | AMOXOR.W |
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103 | AMOAND.W |
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104 | AMOOR.W |
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105 | AMOMIN.W |
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106 | AMOMAX.W |
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107 | AMOMINU.W |
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108 | AMOMAXU.W | Yes (11/11) | Yes (11/11) | |
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109 | 15 | Andrei Tatarnikov | {background:#cfc}. | *RV64A* | LR.D |
110 | 18 | Andrei Tatarnikov | SC.D |
111 | AMOSWAP.D |
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112 | AMOADD.D |
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113 | AMOXOR.D |
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114 | AMOAND.D |
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115 | AMOOR.D |
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116 | AMOMIN.D |
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117 | AMOMAX.D |
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118 | AMOMINU.D |
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119 | AMOMAXU.D | Yes (11/11) | Yes (11/11) | |
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120 | 15 | Andrei Tatarnikov | {background:#ff9}. | *RV32F* | FLW |
121 | 17 | Andrei Tatarnikov | FSW |
122 | FMADD.S |
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123 | FMSUB.S |
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124 | FNMSUB.S |
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125 | FNMADD.S |
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126 | FADD.S |
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127 | FSUB.S |
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128 | FMUL.S |
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129 | FDIV.S |
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130 | FSQRT.S |
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131 | FSGNJ.S |
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132 | FSGNJN.S |
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133 | FSGNJX.S |
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134 | FMIN.S |
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135 | FMAX.S |
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136 | FCVT.W.S |
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137 | FCVT.WU.S |
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138 | FMV.X.W (FMV.X.S) |
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139 | FEQ.S |
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140 | FLT.S |
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141 | FLE.S |
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142 | FCLASS.S |
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143 | FCVT.S.W |
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144 | FCVT.S.WU |
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145 | 35 | Andrei Tatarnikov | FMV.W.X (FMV.S.X) | Yes (26/26) | Partially (8/26) |
146 | 36 | Andrei Tatarnikov | Including (8): |
147 | 35 | Andrei Tatarnikov | FLW |
148 | FSW |
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149 | FEQ_S |
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150 | FLE_S |
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151 | FLT_S |
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152 | FEQ_S |
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153 | FLE_S |
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154 | FLT_S | |
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155 | 17 | Andrei Tatarnikov | {background:#ff9}. | *RV64F* | FCVT.L.S |
156 | FCVT.LU.S |
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157 | FCVT.S.L |
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158 | 36 | Andrei Tatarnikov | FCVT.S.LU | Yes (4/4) | Partially (0/4) | |
159 | 17 | Andrei Tatarnikov | {background:#ff9}. | *RV32D* | FLD |
160 | FSD |
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161 | FMADD.D |
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162 | FMSUB.D |
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163 | FNMSUB.D |
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164 | FNMADD.D |
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165 | FADD.D |
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166 | FSUB.D |
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167 | FMUL.D |
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168 | FDIV.D |
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169 | FSQRT.D |
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170 | FSGNJ.D |
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171 | FSGNJN.D |
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172 | FSGNJX.D |
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173 | FMIN.D |
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174 | FMAX.D |
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175 | FCVT.S.D |
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176 | FCVT.D.S |
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177 | FEQ.D |
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178 | FLT.D |
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179 | FLE.D |
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180 | FCLASS.D |
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181 | FCVT.W.D |
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182 | 1 | Alexander Protsenko | FCVT.WU.D |
183 | FCVT.D.W |
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184 | 36 | Andrei Tatarnikov | FCVT.D.WU | Yes (26/26) | Partially (2/26) |
185 | Including (2): |
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186 | FLD |
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187 | FSD | |
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188 | 18 | Andrei Tatarnikov | {background:#ff9}. | *RV64D* | FCVT.L.D |
189 | 1 | Alexander Protsenko | FCVT.LU.D |
190 | 18 | Andrei Tatarnikov | FMV.X.D |
191 | FCVT.D.L |
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192 | FCVT.D.LU |
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193 | 36 | Andrei Tatarnikov | FMV.D.X | Yes (6/6) | No (0/6) | |
194 | 28 | Andrei Tatarnikov | {background:#ff9}. | *RVC* | C.ADDI4SPN |
195 | C.FLD |
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196 | C.LQ |
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197 | C.LW |
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198 | C.FLW |
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199 | C.LD |
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200 | C.FSD |
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201 | C.SQ |
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202 | C.SW |
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203 | C.FSW |
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204 | C.SD |
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205 | C.NOP |
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206 | C.ADDI |
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207 | C.JAL |
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208 | C.ADDIW |
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209 | C.LI |
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210 | C.ADDI16SP |
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211 | C.LUI |
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212 | C.SRLI |
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213 | C.SRLI64 |
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214 | C.SRAI |
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215 | C.SRAI64 |
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216 | C.ANDI |
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217 | C.SUB |
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218 | C.XOR |
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219 | C.OR |
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220 | C.AND |
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221 | C.SUBW |
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222 | C.ADDW |
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223 | C.J |
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224 | C.BEQZ |
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225 | C.BNEZ |
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226 | C.SLLI |
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227 | C.SLLI64 |
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228 | C.FLDSP |
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229 | C.LQSP |
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230 | C.LWSP |
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231 | C.FLWSP |
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232 | C.LDSP |
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233 | C.JR |
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234 | C.MV |
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235 | C.EBREAK |
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236 | C.JALR |
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237 | C.ADD |
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238 | C.FSDSP |
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239 | C.SQSP |
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240 | C.SWSP |
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241 | C.FSWSP |
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242 | C.SDSP | Yes (49/49) | Partially (36/49) |
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243 | 32 | Andrei Tatarnikov | Excluding (13): |
244 | C.LQ |
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245 | C.FLW |
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246 | C.SQ |
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247 | C.FSW |
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248 | C.NOP |
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249 | C.SRLI64 |
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250 | C.SRAI64 |
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251 | C.SLLI64 |
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252 | C.LQSP |
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253 | C.FLWSP |
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254 | C.EBREAK |
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255 | C.SQSP |
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256 | C.FSWSP | |
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257 | 34 | Andrei Tatarnikov | {background:#fcc}. | *RV64Q* | | No | No | |
258 | 33 | Andrei Tatarnikov | {background:#fcc}. | *RV32V* | VADD |
259 | VSUB |
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260 | VSL |
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261 | VSR |
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262 | VAND |
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263 | VOR |
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264 | VXOR |
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265 | VSEQ |
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266 | VSNE |
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267 | VSLT |
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268 | VSGE |
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269 | VCLIP |
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270 | VCVT |
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271 | VMPOP |
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272 | VMFIRST |
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273 | VEXTRACT |
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274 | VINSERT |
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275 | VMERGE |
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276 | VSELECT |
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277 | VSLIDE |
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278 | VDIV |
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279 | VREM |
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280 | VMUL |
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281 | VMULH |
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282 | VMIN |
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283 | VMAX |
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284 | VSGNJ |
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285 | VSGNJN |
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286 | VSGNJX |
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287 | VSQRT |
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288 | VCLASS |
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289 | VPOPC |
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290 | VADDI |
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291 | VSLI |
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292 | VSRI |
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293 | VANDI |
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294 | VORI |
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295 | VXORI |
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296 | VCLIPI |
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297 | 10 | Andrei Tatarnikov | VMADD |
298 | 7 | Andrei Tatarnikov | VMSUB |
299 | 37 | Andrei Tatarnikov | VNMADD |
300 | VNMSUB | No | No | |
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301 | {background:#ddd}. | Total | | | | |