Instructions supported by MicroTESK for RISC-V¶

The table below shows the status of support for particular instructions in MicroTESK for RISC-V.

Here is the explanation of the meaning of the Specified and Validated columns:

To be supported in MicroTESK, instructions need to be described in formal specifications. The Specified column shows whether specific instructions were described in the specifications.

The instruction semantics described in specifications may be incomplete or invalid. Therefore, instruction specifications must be validated with tests (e.g. ones ported from https://github.com/riscv/riscv-tests). To perform validation, the tests are executed in an ISA simulator constructed on the basis of the specifications. The Validated column shows whether the specifications of specific instructions were validated with tests.

NOTE: Incomplete or invalid semantics of instruction in specifications does not that these instructions cannot be used in test programs. It just prevents using them in tests that require information on the current state of registers and memory (e.g. self-checking tests and constraint-based tests). In general, to generate random tests, only the syntax of instructions is required to be valid while the semantics may be incomplete.

There are three statuses of support based on the two columns and marked with colors:

Instruction table:¶