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Andrei Tatarnikov, 05/09/2018 04:59 PM
RISC-V Instruction Set¶
| Category | RISC-V (Version 2.2) | MicroTESK | ||
| Instructions | Amount | Instructions | Amount | |
| Arithmetic Logic Unit | ADDI SLTI SLTIU XLEN ANDI ORI XORI SRLI SLLI LUI AUIPC ADD SUB SLT SLTU AND OR XOR SLL SRL SRA |
21+ | 0+ | |
| Branch | JAL JALR BEQ BNE BLT BLTU BGE BGEU BGT BGTU BLE BLEU BLT BLTU BGE BGEU |
16 | 0+ | |
| Memory Access | LW LH LHU LB LBU SW SH SB |
8 | 0 | |
| System | CSRRW CSRRS CSRRC CSRRWI CSRRSI CSRRCI RDCYCLE RDTIME RDINSTRET |
9 | 0 | |
| Other | NOP | 1 | NOP | 1 |
| Total: | 65 | 1+ | ||
| 100% |
| 50+% |
| 0+% |
Instructions supported by MicroTESK for RISC-V¶
| Instruction Set | Instructions | Amount |
| RV32I | ? | |
| RV64I | ? | |
| RV32M | ? | |
| RV64M | ? | |
| RV32A | ? | |
| RV64A | ? | |
| RV32F | ? | |
| RV64F | ? | |
| RV32D | 26 | |
| RV64D | FCVT.L.D FCVT.LU.D FMV.X.D FCVT.D.L FCVT.D.LU FMV.D.X |
6 |
| Total |
| Fully supported |
| Stub implementation |
| Unsupported |
Updated by Andrei Tatarnikov almost 6 years ago · 7 revisions