MicroTESK for RISC-V is a MicroTESK based instruction stream generator (ISG) aimed at functional verification of RISC-V microprocessors.
The package can be downloaded from the Files page. Here is an Installation Guide.
The table of RISC-V instructions supported by the ISG is here.
Licensing and Distribution¶
The MicroTESK for RISC-V package (consisting of the MicroTESK core, the RISC-V specifications, and the basic test templates) is distributed under the Apache License, Version 2.0, which implies the freedom to use the software for any purpose (to distribute it, to modify it and to distribute modified versions of the software) under the terms of the license, but requires preservation of the copyright notice and disclaimer.
More facilities can be developed on a commercial basis. We are open for collaboration!
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Issue tracking Details
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MicroTESK for RISC-V 0.1.0 released
MicroTESK for RISC-V 0.1.0 has been released.
MicroTESK for RISC-V 0.0.* re-uploaded
MicroTESK for RISC-V 0.0.* packages have been re-uploaded.
MicroTESK for RISC-V 0.0.9 released
MicroTESK for RISC-V 0.0.9 has been released.
MicroTESK for RISC-V 0.0.8 released
MicroTESK for RISC-V 0.0.8 has been released.
MicroTESK for RISC-V 0.0.7 released
MicroTESK for RISC-V 0.0.7 has been released.
Manager: Alexander Protsenko, Alexander Kamkin, Sergey Smolov
Developer: Alexander Protsenko, Artem Kotsynyak, Mikhail Chupilko, Pavel Putro, Sergey Smolov
Project Creator: Alexander Kamkin, Sergey Smolov