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RISC-V Instruction Set » History » Revision 23

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Andrei Tatarnikov, 07/26/2018 03:30 PM

Instructions supported by MicroTESK for RISC-V

Instruction Set Instructions Specified Validated
RV32I LUI
AUIPC
JAL
JALR
BEQ
BNE
BLT
BGE
BLTU
BGEU
LB
LH
LW
LBU
LHU
SB
SH
SW
ADDI
SLTI
SLTIU
XORI
ORI
ANDI
SLLI
SRLI
SRAI
SLL
SRL
SRA
ADD
SUB
SLT
SLTU
XOR
OR
AND 		Yes (37/37) Yes (37/37)
RV64I LWU
LD
SD
ADDIW
SLLIW
SRLIW
SRAIW
ADDW
SUBW
SLLW
SRLW
SRAW 		Yes (12/12) Yes (12/12)
RV32M MUL
MULH
MULHSU
MULHU
DIV
DIVU
REM
REMU 		Yes (8/8) Yes (8/8)
RV64M MULW
DIVW
DIVUW
REMW
REMUW 		Yes (5/5) Yes (5/5)
RV32A LR.W
SC.W
AMOSWAP.W
AMOADD.W
AMOXOR.W
AMOAND.W
AMOOR.W
AMOMIN.W
AMOMAX.W
AMOMINU.W
AMOMAXU.W 		Yes (11/11) Yes (11/11)
RV64A LR.D
SC.D
AMOSWAP.D
AMOADD.D
AMOXOR.D
AMOAND.D
AMOOR.D
AMOMIN.D
AMOMAX.D
AMOMINU.D
AMOMAXU.D 		Yes (11/11) Yes (11/11)
RV32F FLW
FSW
FMADD.S
FMSUB.S
FNMSUB.S
FNMADD.S
FADD.S
FSUB.S
FMUL.S
FDIV.S
FSQRT.S
FSGNJ.S
FSGNJN.S
FSGNJX.S
FMIN.S
FMAX.S
FCVT.W.S
FCVT.WU.S
FMV.X.W (FMV.X.S)
FEQ.S
FLT.S
FLE.S
FCLASS.S
FCVT.S.W
FCVT.S.WU
FMV.W.X (FMV.S.X) 		Yes (26/26) Partially (?/26)
RV64F FCVT.L.S
FCVT.LU.S
FCVT.S.L
FCVT.S.LU 		Yes (4/4) Partially (?/4)
RV32D FLD
FSD
FMADD.D
FMSUB.D
FNMSUB.D
FNMADD.D
FADD.D
FSUB.D
FMUL.D
FDIV.D
FSQRT.D
FSGNJ.D
FSGNJN.D
FSGNJX.D
FMIN.D
FMAX.D
FCVT.S.D
FCVT.D.S
FEQ.D
FLT.D
FLE.D
FCLASS.D
FCVT.W.D
FCVT.WU.D
FCVT.D.W
FCVT.D.WU 		Yes (26/26) Partially (?/26)
RV64D FCVT.L.D
FCVT.LU.D
FMV.X.D
FCVT.D.L
FCVT.D.LU
FMV.D.X 		Yes (6/6) Partially (?/6)
RVC C.ADDI4SPN (RES, nzimm=0) +
C.FLD (RV32/64) +
C.LQ (RV128) +
C.LW +
C.FLW (RV32) +
C.LD (RV64/128) +
C.FSD (RV32/64) +
C.SQ (RV128) +
C.SW +
C.FSW (RV32) +
C.SD (RV64/128) +
C.NOP +
C.ADDI (HINT, nzimm=0) +
C.JAL (RV32) +
C.ADDIW (RV64/128; RES, rd=0) +
C.LI (HINT, rd=0) +
C.ADDI16SP (RES, nzimm=0) +
C.LUI (RES, nzimm=0; HINT, rd=0) +
C.SRLI (RV32 NSE, nzimm5=1) +
C.SRLI64 (RV128; RV32/64 HINT) +
C.SRAI (RV32 NSE, nzimm5=1) +
C.SRAI64 (RV128; RV32/64 HINT) +
C.ANDI +
C.SUB +
C.XOR +
C.OR +
C.AND +
C.SUBW (RV64/128; RV32 RES) +
C.ADDW (RV64/128; RV32 RES) +
C.J +
C.BEQZ +
C.BNEZ +
C.SLLI (HINT, rd=0; RV32 NSE, nzimm5=1) +
C.SLLI64 (RV128; RV32/64 HINT; HINT, rd=0) +
C.FLDSP (RV32/64) +
C.LQSP (RV128; RES, rd=0) +
C.LWSP (RES, rd=0) +
C.FLWSP (RV32) +
C.LDSP (RV64/128; RES, rd=0) +
C.JR (RES, rs1=0) +
C.MV (HINT, rd=0) +
C.EBREAK +
C.JALR +
C.ADD (HINT, rd=0) +
C.FSDSP (RV32/64) +
C.SQSP (RV128) +
C.SWSP +
C.FSWSP (RV32) +
C.SDSP (RV64/128) + 		49 49
Total
Fully supported
Partially supported
Unsupported

Updated by Andrei Tatarnikov over 6 years ago · 50 revisions