MicroTESK » MicroTESK for RISC-V

What's new?

• Tool Functions: Updated the MicroTESK core to 2.5.0
• Binary Samples: Added binaries samples w/ their C sources (see the arch/riscv/binaries directory)
• Test and Debug: Used QEMU4V 0.3.4 for running tests

Download: https://forge.ispras.ru/projects/microtesk-riscv/files

MicroTESK for RISC-V 0.0.* distribution packages have been re-uploaded to https://forge.ispras.ru/projects/microtesk-riscv/files w/ the build base version having been set.

What's new?

• Specifications: Added the system registers and the related modes
• Specifications: Added sample specifications of some vector instructions (consistent with RISC-V "V" Vector Extension Version 0.7.1)
• Specifications: Fixed bugs in the RV64A instructions
• Specifications: Fixed bugs in the RV32{F,D} instructions (FEQ, FLE, and FLT)
• Test Templates: Added sample test templates for vector instructions
• Test Templates: Changed the structure of directories
• Test Templates: Fixed the Torture-like template (synthetics/rvxxx)
• Tool Functions: Moved the branch data generators to TestBase
• Test and Debug: Used QEMU4V 0.3.3 for running tests

Download: https://forge.ispras.ru/projects/microtesk-riscv/files

What's new?

• Specifications: Address translation for the Sv32, Sv39, and Sv48 modes
• Test Templates: Test templates for address translation
• Tests: Test suite uses QEMU4V 0.3.2

Download: https://forge.ispras.ru/projects/microtesk-riscv/files

What's new?

• Specifications: Vector extension (draft)

Download: https://forge.ispras.ru/projects/microtesk-riscv/files

What's new?

• Specifications: Bug fixes in floating-point instructions
• Tool Functions: Updated MicroTESK core

Download: http://forge.ispras.ru/projects/microtesk-riscv/files

What's new?

• Specifications: Bug fixes
• Test Templates: Test templates for generating torture tests
• Test Templates: Test templates for validating floating-point instructions
• Tool Functions: Improved floating-point support
• Tool Functions: Improved register allocation mechanism
• Tool Functions: Support for operations with dynamic immediate values in test templates (_AND, _OR, _XOR, _ADD, _SUB, _PLUS, _MINUS, _NOT, _SLL)
• Tests: Improved Make scripts for running test templates
• Tests: Specification code coverage is measured
• Tests: Test suite uses QEMU4V 0.2.2

Download: http://forge.ispras.ru/projects/microtesk-riscv/files

What's new?

• Specifications: Support for RV32C and RV64C
• Specifications: Bug fixes
• Test Templates: RISC-V validation tests rv32uc/rvc and rv64uc/rvc
• Test Templates: Test templates are split into groups being located in separate folders
• Tests: Test suite uses QEMU4V 0.1.1

Download: http://forge.ispras.ru/projects/microtesk-riscv/files

What's new?

• Specifications: System registers and system instructions
• Specifications: Bug fixes and improvements
• Test Templates: Automatically generated test templates
• Test Templates: BPU test templates that use the Branch engine
• Test Templates: Libraries to describe initialization/finalization code
• Test Templates: Updated linker settings
• Test Templates: Test templates to validate user-level instruction
• Test Templates: More demo test templates
• Tool Functions: Support for global labels, numeric labels, and weak symbols
• Tool Functions: Test data iterator functionality
• Tool Functions: Support for automated generation of test templates
• Tests: Test suite uses QEMU for RISC-V 0.2.1
• Tests: Test suite uses Spike (RISC-V ISA Simulator)
• Tests: Trace Matcher 0.1.8 is applied

Download: http://forge.ispras.ru/projects/microtesk-riscv/files

What's new?

• Specifications: New pseudo instructions for RV32I, RV32F, and RV32D
• Test Templates: 5 new test templates

Download: http://forge.ispras.ru/projects/microtesk-riscv/files