What's new?
- Specifications: Added system registers and the related modes
- Specifications: Added sample specifications of some vector instructions (consistent with RISC-V "V" Vector Extension Version 0.7.1)
- Specifications: Fixed bugs in
RV64A instructions
- Specifications: Fixed bugs in
RV32{F,D} instructions (FEQ, FLE, and FLT)
- Test Templates: Added sample test templates for vector instructions
- Test Templates: Changed structure of directories
- Test Templates: Fixed a Torture-like template (
synthetics/rvxxx)
- Tool Functions: Moved branch data generators to TestBase
- Tests: Test suite uses QEMU4V 0.3.3
Download: https://forge.ispras.ru/projects/microtesk-riscv/files
What's new?
- Specifications: Bug fixes
- Test Templates: Test templates for generating torture tests
- Test Templates: Test templates for validating floating-point instructions
- Tool Functions: Improved floating-point support
- Tool Functions: Improved register allocation mechanism
- Tool Functions: Support for operations with dynamic immediate values in test templates (
_AND, _OR, _XOR, _ADD, _SUB, _PLUS, _MINUS, _NOT, _SLL)
- Tests: Improved Make scripts for running test templates
- Tests: Specification code coverage is measured
- Tests: Test suite uses QEMU4V 0.2.2
Download: http://forge.ispras.ru/projects/microtesk-riscv/files
What's new?
- Specifications: Support for
RV32C and RV64C
- Specifications: Bug fixes
- Test Templates: RISC-V validation tests
rv32uc/rvc and rv64uc/rvc
- Test Templates: Test templates are split into groups being located in separate folders
- Tests: Test suite uses QEMU4V 0.1.1
Download: http://forge.ispras.ru/projects/microtesk-riscv/files
What's new?
- Specifications: System registers and system instructions
- Specifications: Bug fixes and improvements
- Test Templates: Automatically generated test templates
- Test Templates: BPU test templates that use the Branch engine
- Test Templates: Libraries to describe initialization/finalization code
- Test Templates: Updated linker settings
- Test Templates: Test templates to validate user-level instruction
- Test Templates: More demo test templates
- Tool Functions: Support for global labels, numeric labels, and weak symbols
- Tool Functions: Test data iterator functionality
- Tool Functions: Support for automated generation of test templates
- Tests: Test suite uses QEMU for RISC-V 0.2.1
- Tests: Test suite uses Spike (RISC-V ISA Simulator)
- Tests: Trace Matcher 0.1.8 is applied
Download: http://forge.ispras.ru/projects/microtesk-riscv/files
MicroTESK for RISC-V 0.0.9 released
