MicroTESK for RISC-V 0.0.8 has been released:
- Specifications: Address translation for the Sv32, Sv39, and Sv48 modes
- Test Templates: Test templates for address translation
- Tests: Test suite uses QEMU4V 0.3.2
MicroTESK for RISC-V can be downloaded from https://forge.ispras.ru/projects/microtesk-riscv/files
MicroTESK for RISC-V 0.0.5 has been released:
- Specifications: Bug fixes
- Test Templates: Test templates for generating torture tests
- Test Templates: Test templates for validating floating-point instructions
- Tool Functions: Improved floating-point support
- Tool Functions: Improved register allocation mechanism
- Tool Functions: Support for operations with dynamic immediate values in test templates (
_AND
, _OR
, _XOR
, _ADD
, _SUB
, _PLUS
, _MINUS
, _NOT
, _SLL
)
- Tests: Improved Make scripts for running test templates
- Tests: Specification code coverage is measured
- Tests: Test suite uses QEMU4V 0.2.2
MicroTESK for RISC-V can be downloaded from http://forge.ispras.ru/projects/microtesk-riscv/files
MicroTESK for RISC-V 0.0.4 has been released:
- Specifications: Support for
RV32C
and RV64C
- Specifications: Bug fixes
- Test Templates: RISC-V validation tests
rv32uc/rvc
and rv64uc/rvc
- Test Templates: Test templates are split into groups being located in separate folders
- Tests: Test suite uses QEMU4V 0.1.1
MicroTESK for RISC-V can be downloaded from http://forge.ispras.ru/projects/microtesk-riscv/files
MicroTESK for RISC-V 0.0.3 has been released:
- Specifications: System registers and system instructions
- Specifications: Bug fixes and improvements
- Test Templates: Automatically generated test templates
- Test Templates: BPU test templates that use the Branch engine
- Test Templates: Libraries to describe initialization/finalization code
- Test Templates: Updated linker settings
- Test Templates: Test templates to validate user-level instruction
- Test Templates: More demo test templates
- Tool Functions: Support for global labels, numeric labels, and weak symbols
- Tool Functions: Test data iterator functionality
- Tool Functions: Support for automated generation of test templates
- Tests: Test suite uses QEMU for RISC-V 0.2.1
- Tests: Test suite uses Spike (RISC-V ISA Simulator)
- Tests: Trace Matcher 0.1.8 is applied
MicroTESK for RISC-V can be downloaded from http://forge.ispras.ru/projects/microtesk-riscv/files
MicroTESK for RISC-V 0.0.1 has been released:
- Specifications: Instruction set of RISC-V: RV32I, RV64I, RV32M, RV64M, RV32A, RV64A, RV32F, RV64F, RV32D, RV64D
- Test Templates: 20 test templates
MicroTESK for RISC-V can be downloaded from http://forge.ispras.ru/projects/microtesk-riscv/files