Actions
Bug #9253
closedru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_07_01_02_1: no viable alternative
Start date:
08/31/2018
Due date:
% Done:
0%
Estimated time:
Detected in build:
svn
Platform:
Published in build:
Description
module test; input in1, in2; output out1; nor (highz1,strong0) n1(out1,in1,in2); endmodule
Actions