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Bug #9252

closed

ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_05_01_05_2: Cannot convert a real to a bitvector

Added by Alexander Kamkin about 6 years ago. Updated about 4 years ago.

Status:
Closed
Priority:
Normal
Assignee:
Alexander Kamkin
Target version:
0.1
Start date:
08/31/2018
Due date:
% Done:

100%

Estimated time:
Detected in build:
master
Platform:
Published in build:
0.1.3-beta-201002

Description

Support for real variables.

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