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Bug #9231

closed

ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PI_BUS_single_master_master2: java.lang.NullPointerException

Added by Sergey Smolov over 5 years ago. Updated over 5 years ago.

Status:
Closed
Priority:
High
Assignee:
Sergey Smolov
Target version:
0.1
Start date:
08/17/2018
Due date:
% Done:

100%

Estimated time:
Detected in build:
master
Platform:
Published in build:

Description

The test case produces the following exception:

java.lang.NullPointerException
    at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_binary_operation(VerilogTreeBuilder.java:6931)
    at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_operation(VerilogTreeBuilder.java:6225)
    at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_expression(VerilogTreeBuilder.java:6060)
    at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_binary_operation(VerilogTreeBuilder.java:6923)
    at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_operation(VerilogTreeBuilder.java:6225)
    at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_expression(VerilogTreeBuilder.java:6060)
    at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_if_statement(VerilogTreeBuilder.java:4671)
    at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_statement(VerilogTreeBuilder.java:4087)
    at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_block_statement(VerilogTreeBuilder.java:5171)
    at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_statement(VerilogTreeBuilder.java:4117)
    at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_case_statement_item(VerilogTreeBuilder.java:5513)
    at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_case_statement(VerilogTreeBuilder.java:4835)
    at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_statement(VerilogTreeBuilder.java:4097)
    at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_block_statement(VerilogTreeBuilder.java:5171)
    at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_statement(VerilogTreeBuilder.java:4117)
    at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_delayed_statement(VerilogTreeBuilder.java:4620)
    at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_statement(VerilogTreeBuilder.java:4077)
    at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_process(VerilogTreeBuilder.java:3202)
    at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_item(VerilogTreeBuilder.java:946)
    at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_module(VerilogTreeBuilder.java:674)
    at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.ast_root(VerilogTreeBuilder.java:516)
    at ru.ispras.verilog.parser.grammar.VerilogTreeBuilder.startRule(VerilogTreeBuilder.java:466)
    at ru.ispras.verilog.parser.VerilogFrontend.startBuilder(VerilogFrontend.java:250)
    at ru.ispras.verilog.parser.VerilogFrontend.startBuilder(VerilogFrontend.java:255)
    at ru.ispras.verilog.parser.VerilogFrontend.start(VerilogFrontend.java:270)
    at ru.ispras.verilog.parser.VerilogFrontend.start(VerilogFrontend.java:274)
    at ru.ispras.verilog.parser.VerilogTranslator.start(VerilogTranslator.java:168)
    at ru.ispras.verilog.parser.sample.VerilogPrinter.main(VerilogPrinter.java:45)
    at ru.ispras.verilog.parser.VerilogBenchmarkTest.runTest(VerilogBenchmarkTest.java:72)
    at ru.ispras.verilog.parser.VerilogBenchmarkTest.runTest(VerilogBenchmarkTest.java:58)
    at ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PI_BUS_single_master_master2(VerilogTexas97TestCase.java:515)

The tool error log is:

ERROR: /home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PI_BUS/multi_master/master2.v line 155:23 no viable alternative at input ')'
DEBUG: Expanding macro '3'b000' ...
DEBUG: End of the token source 'null'
ERROR: /home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PI_BUS/multi_master/master2.v line 165:27 no viable alternative at input ')'
DEBUG: Expanding macro '3'b101' ...
DEBUG: End of the token source 'null'
ERROR: /home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PI_BUS/multi_master/master2.v line 167:27 no viable alternative at input ')'
ERROR: /home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PI_BUS/multi_master/master2.v line 167:42 no viable alternative at input ')'
DEBUG: Expanding macro '3'b011' ...
DEBUG: End of the token source 'null'
ERROR: /home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PI_BUS/multi_master/master2.v line 176:23 no viable alternative at input ')'
DEBUG: Expanding macro '3'b011' ...
DEBUG: End of the token source 'null'
DEBUG: Expanding macro '3'b100' ...
DEBUG: End of the token source 'null'
DEBUG: Expanding macro '3'b100' ...
DEBUG: End of the token source 'null'
ERROR: /home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PI_BUS/multi_master/master2.v line 192:23 no viable alternative at input ')'
DEBUG: Expanding macro '3'b000' ...
DEBUG: End of the token source 'null'
ERROR: /home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PI_BUS/multi_master/master2.v line 202:27 no viable alternative at input ')'
DEBUG: Expanding macro '3'b101' ...
DEBUG: End of the token source 'null'
ERROR: /home/ssedai/projects/veritrans/src/test/verilog/texas97-tests/PI_BUS/multi_master/master2.v line 204:25 no viable alternative at input ')'
DEBUG: Expanding macro '3'b100' ...
DEBUG: End of the token source 'null'
DEBUG: Expanding macro '3'b001' ...
DEBUG: End of the token source 'null'
DEBUG: Expanding macro '3'b000' ...
DEBUG: End of the token source 'null'
DEBUG: Expanding macro '3'b101' ...
DEBUG: End of the token source 'null'
DEBUG: Expanding macro '3'b010' ...
DEBUG: End of the token source 'null'
DEBUG: Expanding macro '3'b001' ...
DEBUG: End of the token source 'null'
DEBUG: Expanding macro '2'b00' ...
DEBUG: End of the token source 'null'
DEBUG: Expanding macro '2'b00' ...
DEBUG: End of the token source 'null'
DEBUG: Expanding macro '2'b01' ...
DEBUG: End of the token source 'null'
DEBUG: Expanding macro '2'b01' ...
DEBUG: End of the token source 'null'
DEBUG: Expanding macro '2'b10' ...
DEBUG: End of the token source 'null'
DEBUG: Expanding macro '2'b10' ...
DEBUG: End of the token source 'null'
DEBUG: Expanding macro '2'b00' ...
DEBUG: End of the token source 'null'
DEBUG: Expanding macro '2'b01' ...
DEBUG: End of the token source 'null'
DEBUG: Expanding macro '2'b10' ...
DEBUG: End of the token source 'null'
ERROR: ru/ispras/verilog/parser/grammar/VerilogTreeBuilder.g: node from after line 155:12 no viable alternative at input ')'

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