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Bug #9165

closed

Incorrect parameter value calculation at hierarchical Verilog description

Added by Sergey Smolov over 5 years ago. Updated over 5 years ago.

Status:
Closed
Priority:
High
Assignee:
Alexander Kamkin
Target version:
0.1
Start date:
07/26/2018
Due date:
% Done:

0%

Estimated time:
Detected in build:
master
Platform:
Published in build:

Description

See the related Bug*Test5TestCase.java for more details. Look at "outreg" array element size - it should be 256 bit rather than 32.

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