Bug #8865: VerilogIeeeTestCase.runTest_19_11_00_1: java.lang.IllegalArgumentException: Declaration=DECLARATION(), parent=MODULE(m2) - Verilog Translator - Open-Source Projects

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Bug #8865

closed

VerilogIeeeTestCase.runTest_19_11_00_1: java.lang.IllegalArgumentException: Declaration=DECLARATION(), parent=MODULE(m2)

Added by Sergey Smolov almost 6 years ago. Updated over 5 years ago.

Status:

Closed

Priority:

Normal

Assignee:

Alexander Kamkin

Target version:

0.1

Start date:

05/07/2018

Due date:

% Done:

Estimated time:

Detected in build:

master

Platform:

Published in build:

Description

The stack trace:

java.lang.IllegalArgumentException: Declaration=DECLARATION(), parent=MODULE(m2)
    at ru.ispras.fortress.util.InvariantChecks.checkTrue(InvariantChecks.java:53)
    at ru.ispras.fortress.util.InvariantChecks.checkNotNull(InvariantChecks.java:109)
    at ru.ispras.verilog.parser.model.util.ModelUtils.getVariable(ModelUtils.java:154)
    at ru.ispras.verilog.parser.model.util.ModelUtils.getVariable(ModelUtils.java:169)
    at ru.ispras.verilog.parser.elaborator.VerilogElaborator.createBindings(VerilogElaborator.java:508)
    at ru.ispras.verilog.parser.elaborator.VerilogElaborator.createBindings(VerilogElaborator.java:481)
    at ru.ispras.verilog.parser.elaborator.VerilogElaborator.expand(VerilogElaborator.java:275)
    at ru.ispras.verilog.parser.elaborator.VerilogElaborator.start(VerilogElaborator.java:181)
    at ru.ispras.verilog.parser.VerilogSyntaxBackends.start(VerilogSyntaxBackends.java:56)
    at ru.ispras.verilog.parser.VerilogTranslator.start(VerilogTranslator.java:163)
    at ru.ispras.verilog.parser.sample.VerilogPrinter.main(VerilogPrinter.java:45)
    at ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest(VerilogIeeeTestCase.java:1813)
    at ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest(VerilogIeeeTestCase.java:1799)
    at ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_19_11_00_1(VerilogIeeeTestCase.java:1786)

The target Verilog module:

`begin_keywords "1364-2001" // use IEEE Std 1364-2001 Verilog keywords
module m2;
  wire [63:0] uwire; // OK: "uwire" is not a keyword in 1364-2001
 // ...
endmodule
`end_keywords