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Bug #8853

closed

VerilogIeeeTestCase.runTest_05_02_01_2: java.lang.IllegalArgumentException

Added by Sergey Smolov almost 6 years ago. Updated over 5 years ago.

Status:
Closed
Priority:
Normal
Assignee:
Alexander Kamkin
Target version:
0.1
Start date:
05/07/2018
Due date:
% Done:

0%

Estimated time:
Detected in build:
master
Platform:
Published in build:

Description

The stack trace:

java.lang.IllegalArgumentException
    at ru.ispras.fortress.util.InvariantChecks.checkTrue(InvariantChecks.java:53)
    at ru.ispras.fortress.util.InvariantChecks.checkTrue(InvariantChecks.java:38)
    at ru.ispras.fortress.util.InvariantChecks.checkNotNull(InvariantChecks.java:95)
    at ru.ispras.verilog.parser.processor.VerilogExprTransformer$3.apply(VerilogExprTransformer.java:210)
    at ru.ispras.fortress.transformer.NodeTransformer.applyRule(NodeTransformer.java:166)
    at ru.ispras.fortress.transformer.NodeTransformer.onOperationEnd(NodeTransformer.java:226)
    at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:173)
    at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
    at ru.ispras.fortress.expression.ExprTreeWalker.visit(ExprTreeWalker.java:93)
    at ru.ispras.fortress.transformer.NodeTransformer.walk(NodeTransformer.java:54)
    at ru.ispras.fortress.transformer.Transformer.transform(Transformer.java:230)
    at ru.ispras.verilog.parser.processor.VerilogExprTransformer.transform(VerilogExprTransformer.java:62)
    at ru.ispras.verilog.parser.elaborator.VerilogTransformer.transform(VerilogTransformer.java:151)
    at ru.ispras.verilog.parser.elaborator.VerilogTransformer.transform(VerilogTransformer.java:184)
    at ru.ispras.verilog.parser.elaborator.VerilogTransformer.onAssignStatementBegin(VerilogTransformer.java:78)
    at ru.ispras.verilog.parser.walker.VerilogNodeVisitor$3.onBegin(VerilogNodeVisitor.java:265)
    at ru.ispras.verilog.parser.walker.VerilogNodeVisitor.onBegin(VerilogNodeVisitor.java:700)
    at ru.ispras.verilog.parser.core.TreeWalker.onBegin(TreeWalker.java:100)
    at ru.ispras.verilog.parser.core.TreeWalker.start(TreeWalker.java:85)
    at ru.ispras.verilog.parser.elaborator.VerilogTransformer.run(VerilogTransformer.java:53)
    at ru.ispras.verilog.parser.elaborator.VerilogVariableSubstitutor.transform(VerilogVariableSubstitutor.java:44)
    at ru.ispras.verilog.parser.elaborator.VerilogInstantiator.instantiateProcess(VerilogInstantiator.java:88)
    at ru.ispras.verilog.parser.elaborator.VerilogDesign$1$1.next(VerilogDesign.java:185)
    at ru.ispras.verilog.parser.elaborator.VerilogDesign$1$1.next(VerilogDesign.java:173)
    at ru.ispras.verilog.parser.sample.VerilogDesignPrinter.start(VerilogDesignPrinter.java:36)
    at ru.ispras.verilog.parser.VerilogDesignBackends.start(VerilogDesignBackends.java:56)
    at ru.ispras.verilog.parser.VerilogTranslator.start(VerilogTranslator.java:169)
    at ru.ispras.verilog.parser.sample.VerilogPrinter.main(VerilogPrinter.java:45)
    at ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest(VerilogIeeeTestCase.java:1813)
    at ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest(VerilogIeeeTestCase.java:1799)
    at ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_05_02_01_2(VerilogIeeeTestCase.java:293)

The target Verilog module:

// IEEE Std 1364-2005
//   5. Expressions
//    5.2 Operands
//      5.2.1 Vector bit-select and part-select addressing
module test;
  reg [31: 0] big_vect;
  reg [0 :31] little_vect;
  reg [63: 0] dword;
  integer sel;

  initial begin
    big_vect[ 0 +: 8]    = 8'b1010_1010; // == big_vect[ 7 : 0]
    big_vect[15 -: 8]    = 8'b1010_1010; // == big_vect[15 : 8]
    little_vect[ 0 +: 8] = 8'b1010_1010; // == little_vect[0 : 7]
    little_vect[15 -: 8] = 8'b1010_1010; // == little_vect[8 :15]
    dword[8*sel +: 8]    = 8'b1010_1010; // variable part-select with fixed width
  end
endmodule

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