Verilog Translator

Here is the tool log for test_19_04_00_3.v module:

 runTest_19_04_00_3 STANDARD_ERROR
    L:\work\veritrans\src\test\verilog\ieee-tests\test_19_04_00_3.v line 36:6 mismatched input 'initial' expecting LPAREN
    ru\ispras\verilog\parser\grammar\VerilogTreeBuilder.g: node from after line 35:11 required (...)+ loop did not match anything at input 'initial'
    ru\ispras\verilog\parser\grammar\VerilogTreeBuilder.g: node from after line 35:11 mismatched tree node: UP expecting AST_ATTRIBUTES

ru.ispras.verilog.parser.VerilogIeeeTestCase > runTest_19_04_00_3 STANDARD_OUT
    Starting the backend 'static-checker'...
    Instance: null
    Starting the backend 'printer'...
    module test();
      initial
        /* DECL: null */
        $display(0010001000101110011001000110010101101110011010010110011001100101011001000010000001110100011011110110111000100000011101000110110001110101011100110110010101110010010111110111010001110011011000010110110000100000001011000110101101100011011011110110110001100010010111110110010001101110011011110110001101100101011100110010000000101100011010110110001101101111011011000110001001011111011101000111001101110010011010010110011000100010);
      /* DECL: null */
      real_last null
      (
      );
    endmodule

    Starting the backend 'design-elaborator'...
    Expanding node 'MODULE(test)'...
    Bindings: {}
    Variables: {}
    Module 'real_last' cannot be found

Unexpected exception thrown.

To reproduce the bug uncomment the runTest_19_04_00_3 method (line 1759) at VerilogIeeeTestCase