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Task #5107

closed

[cfg] Реализовать VhdlExpressionPrinter

Added by Sergey Smolov over 9 years ago. Updated over 9 years ago.

Status:
Closed
Priority:
Normal
Assignee:
Category:
-
Target version:
Start date:
07/21/2014
Due date:
% Done:

100%

Estimated time:
Detected in build:
svn
Published in build:
r618

Description

Реализовать печать выражений VHDL по образу и подобию VerilogExpressionPrinter из проекта Verilog Translator.

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