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Bug #10510

open

ERROR: [Internal] Bit vector sizes do not match: 32 != 2.

Added by Sergey Smolov about 4 years ago. Updated about 4 years ago.

Status:
New
Priority:
Normal
Assignee:
Alexander Kamkin
Target version:
0.1
Start date:
10/01/2020
Due date:
% Done:

0%

Estimated time:
Detected in build:
git
Platform:
Published in build:

Description

java.lang.IllegalArgumentException: Bit vector sizes do not match: 32 != 2.
    at ru.ispras.fortress.data.types.bitvector.BitVectorMath.checkEqualSize(BitVectorMath.java:1255)
    at ru.ispras.fortress.data.types.bitvector.BitVectorMath.transform(BitVectorMath.java:1231)
    at ru.ispras.fortress.data.types.bitvector.BitVectorMath.add(BitVectorMath.java:869)
    at ru.ispras.fortress.data.types.bitvector.BitVectorMath.sub(BitVectorMath.java:888)
    at ru.ispras.verilog.parser.interpreter.VerilogOperations$10.calculate(VerilogOperations.java:222)
    at ru.ispras.fortress.calculator.OperationGroup.calculate(OperationGroup.java:141)
    at ru.ispras.fortress.transformer.Reducer$OperationRule.apply(Reducer.java:147)
    at ru.ispras.fortress.transformer.NodeTransformer.applyRule(NodeTransformer.java:173)
    at ru.ispras.fortress.transformer.NodeTransformer.updateNode(NodeTransformer.java:183)
    at ru.ispras.fortress.transformer.NodeTransformer.onOperationEnd(NodeTransformer.java:231)
    at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:173)
    at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
    at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:160)
    at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
    at ru.ispras.fortress.expression.ExprTreeWalker.visit(ExprTreeWalker.java:93)
    at ru.ispras.fortress.transformer.NodeTransformer.walk(NodeTransformer.java:54)
    at ru.ispras.fortress.transformer.Reducer.reduce(Reducer.java:183)
    at ru.ispras.verilog.parser.interpreter.VerilogCalculator.evaluate(VerilogCalculator.java:67)
    at ru.ispras.verilog.parser.elaborator.VerilogElaborator.evaluate(VerilogElaborator.java:1161)
    at ru.ispras.verilog.parser.elaborator.VerilogElaborator.defineParameter(VerilogElaborator.java:1073)
    at ru.ispras.verilog.parser.elaborator.VerilogElaborator.createVariableAndBinding(VerilogElaborator.java:526)
    at ru.ispras.verilog.parser.elaborator.VerilogElaborator.createVariablesAndBindings(VerilogElaborator.java:910)
    at ru.ispras.verilog.parser.elaborator.VerilogElaborator.createVariablesAndBindings(VerilogElaborator.java:883)
    at ru.ispras.verilog.parser.elaborator.VerilogElaborator.expand(VerilogElaborator.java:330)
    at ru.ispras.verilog.parser.elaborator.VerilogElaborator.start(VerilogElaborator.java:231)
    at ru.ispras.verilog.parser.VerilogSyntaxBackends.start(VerilogSyntaxBackends.java:55)
    at ru.ispras.verilog.parser.VerilogTranslator.start(VerilogTranslator.java:212)
    at ru.ispras.verilog.parser.sample.VerilogPrinter.main(VerilogPrinter.java:45)
    at ru.ispras.verilog.parser.util.VerilogBenchmarkTest.runTest(VerilogBenchmarkTest.java:62)
    at ru.ispras.verilog.parser.VerilogIwlsTestSuite.runTest_risc_defgh(VerilogIwlsTestSuite.java:1692)
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