Verilog Translator

When processing the hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v module, the following errors appear:

ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 76:13 no viable alternative at input '['
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 77:22 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 78:22 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 79:21 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 80:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 81:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 82:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 83:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 84:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 85:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 86:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 87:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 88:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 89:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 90:19 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 91:18 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 95:22 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 96:22 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 97:21 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 98:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 99:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 100:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 101:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 102:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 103:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 104:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 105:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 106:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 107:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 108:19 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 109:18 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 113:22 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 114:22 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 115:21 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 116:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 117:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 118:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 119:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 120:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 121:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 122:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 123:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 124:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 125:20 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 126:19 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 127:18 mismatched input '=' expecting LPAREN
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 1:0 extraneous input '\' expecting KW_END
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 1:0 extraneous input '\' expecting KW_END
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 1:0 mismatched input '\' expecting KW_END
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 245:17 mismatched input '=' expecting COLON
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 245:33 missing COLON at ';'
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 246:14 mismatched input '=' expecting COLON
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 246:25 missing COLON at ';'
ERROR: L:\work\veritrans\src\test\verilog\hdl-benchmarks\hdl\iwls05\opencores\rtl\systemcaes\subbytes.v line 247:2 extraneous input 'end' expecting KW_ENDCASE
ERROR: ru\ispras\verilog\parser\grammar\VerilogTreeBuilder.g: node from after line 73:0 mismatched tree node: <unexpected: [@6101,3705:3705='[',<214>,76:13], resync=data_reg_128> expecting <UP>
ERROR: ru\ispras\verilog\parser\grammar\VerilogTreeBuilder.g: node from after line 76:40 mismatched tree node: AST_STRENGTH expecting <UP>

The problem is connected with the following macro in Verilog:

`define assign_array_to_128 \
    data_reg_128[127:120]=data_reg_var[0]; \
    data_reg_128[119:112]=data_reg_var[1];  \
    data_reg_128[111:104]=data_reg_var[2];   \
    data_reg_128[103:96]=data_reg_var[3];       \
    data_reg_128[95:88]=data_reg_var[4];        \
    data_reg_128[87:80]=data_reg_var[5];         \
    data_reg_128[79:72]=data_reg_var[6];          \
    data_reg_128[71:64]=data_reg_var[7];           \
    data_reg_128[63:56]=data_reg_var[8];            \
    data_reg_128[55:48]=data_reg_var[9];             \
    data_reg_128[47:40]=data_reg_var[10];              \
    data_reg_128[39:32]=data_reg_var[11];               \
    data_reg_128[31:24]=data_reg_var[12];                \
    data_reg_128[23:16]=data_reg_var[13];                 \
    data_reg_128[15:8]=data_reg_var[14];                  \
    data_reg_128[7:0]=data_reg_var[15];