Retrascope

This error appears in VcegarCC2ProcModCfgGraphMlTestCase and VcegarCC3ProcModCfgGraphMlTestCase of the Retrascope-MC-Benchmark project.
Error log:

java.lang.IllegalArgumentException: 0 must be > 0

at ru.ispras.fortress.util.InvariantChecks.checkGreaterThanZero(InvariantChecks.java:159)
at ru.ispras.fortress.data.DataType.bitVector(DataType.java:71)
at ru.ispras.fortress.transformer.ConstCastRuleSet.castWrongBvOperands(ConstCastRuleSet.java:295)
at ru.ispras.fortress.transformer.ConstCastRuleSet.access$1300(ConstCastRuleSet.java:38)
at ru.ispras.fortress.transformer.ConstCastRuleSet$10.isApplicable(ConstCastRuleSet.java:209)
at ru.ispras.fortress.transformer.ConstCastRuleSet$CastConstRule.isApplicable(ConstCastRuleSet.java:78)
at ru.ispras.fortress.transformer.NodeTransformer.applyRule(NodeTransformer.java:165)
at ru.ispras.fortress.transformer.NodeTransformer.onOperationEnd(NodeTransformer.java:226)
at ru.ispras.fortress.expression.ExprTreeWalker.visitOperation(ExprTreeWalker.java:173)
at ru.ispras.fortress.expression.ExprTreeWalker.visitNode(ExprTreeWalker.java:123)
at ru.ispras.fortress.expression.ExprTreeWalker.visit(ExprTreeWalker.java:93)
at ru.ispras.fortress.transformer.NodeTransformer.walk(NodeTransformer.java:54)
at ru.ispras.fortress.transformer.TypeConversion.castConstants(TypeConversion.java:76)
at ru.ispras.fortress.transformer.TypeConversion.castConstants(TypeConversion.java:91)
at ru.ispras.retrascope.parser.verilog.VerilogCfgProcessBuilder.transformNode(VerilogCfgProcessBuilder.java:256)
at ru.ispras.retrascope.parser.verilog.VerilogCfgProcessBuilder.parseAssignment(VerilogCfgProcessBuilder.java:424)
at ru.ispras.retrascope.parser.verilog.VerilogCfgProcessBuilder.onAssignStatementBegin(VerilogCfgProcessBuilder.java:584)
at ru.ispras.verilog.parser.walker.VerilogNodeVisitor$3.onBegin(VerilogNodeVisitor.java:265)
at ru.ispras.verilog.parser.walker.VerilogNodeVisitor.onBegin(VerilogNodeVisitor.java:700)
at ru.ispras.verilog.parser.core.TreeWalker.onBegin(TreeWalker.java:100)
at ru.ispras.verilog.parser.core.TreeWalker.start(TreeWalker.java:79)
at ru.ispras.retrascope.parser.verilog.VerilogCfgBuilder.start(VerilogCfgBuilder.java:82)
at ru.ispras.verilog.parser.VerilogDesignBackends.start(VerilogDesignBackends.java:56)
at ru.ispras.verilog.parser.VerilogTranslator.start(VerilogTranslator.java:169)
at ru.ispras.retrascope.parser.verilog.VerilogParser.parse(VerilogParser.java:103)
at ru.ispras.retrascope.parser.basis.HdlParser.start(HdlParser.java:112)
at ru.ispras.retrascope.basis.Engine.start(Engine.java:217)
at ru.ispras.retrascope.basis.ToolChain.start(ToolChain.java:111)
at ru.ispras.retrascope.basis.Engine.start(Engine.java:217)
at ru.ispras.retrascope.Retrascope$ToolRun.start(Retrascope.java:215)
at ru.ispras.retrascope.Retrascope.main(Retrascope.java:456)
at ru.ispras.retrascope.Retrascope.main(Retrascope.java:373)
...

Corresponding Verilog:

src/main/verilog/vcegar-benchmarks/cache_coherence/modified/two_processor_bin_2_mod.v
src/main/verilog/vcegar-benchmarks/cache_coherence/modified/three_processor_bin_2_mod.v