Bug #8912
closed
file ram.smv: line 332: variable is assigned more than once: m_ram.mem0
Added by Sergey Smolov over 6 years ago.
Updated over 5 years ago.
Category:
Engine (Transformer)
Published in build:
1.1.1-beta-190722
Description
The nuXmv model checker fails to elaborate designs that assign same variable in different processes.
See ram.v & fifo.v Verilog modules.
- Assignee set to Sergey Smolov
- Related to Feature #9039: Support for designs that assign to variable more than once added
- Assignee changed from Sergey Smolov to Mikhail Lebedev
- Status changed from New to Resolved
- Assignee changed from Mikhail Lebedev to Sergey Smolov
- % Done changed from 0 to 100
- Category set to Engine (Transformer)
- Status changed from Resolved to Closed
- Published in build set to 1.1.1-beta-190722
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