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Bug #8912

closed

file ram.smv: line 332: variable is assigned more than once: m_ram.mem0

Added by Sergey Smolov over 6 years ago. Updated over 5 years ago.

Status:
Closed
Priority:
Normal
Assignee:
Sergey Smolov
Category:
Engine (Transformer)
Target version:
1.0
Start date:
06/01/2018
Due date:
% Done:

100%

Estimated time:
Detected in build:
master
Platform:
Published in build:
1.1.1-beta-190722

Description

The nuXmv model checker fails to elaborate designs that assign same variable in different processes.
See ram.v & fifo.v Verilog modules.

Related issues 1 (0 open — 1 closed)

Related to Retrascope - Feature #9039: Support for designs that assign to variable more than onceClosedSergey Smolov06/29/2018

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 #1

Updated by Sergey Smolov over 6 years ago

  • Assignee set to Sergey Smolov
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 #2

Updated by Sergey Smolov over 6 years ago

  • Related to Feature #9039: Support for designs that assign to variable more than once added
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 #3

Updated by Sergey Smolov over 6 years ago

  • Assignee changed from Sergey Smolov to Mikhail Lebedev
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 #4

Updated by Sergey Smolov over 6 years ago

  • Status changed from New to Resolved
  • Assignee changed from Mikhail Lebedev to Sergey Smolov
  • % Done changed from 0 to 100

Fixed in 7cf2a84e

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 #5

Updated by Sergey Smolov almost 6 years ago

  • Category set to Engine (Transformer)
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 #6

Updated by Sergey Smolov over 5 years ago

  • Status changed from Resolved to Closed
  • Published in build set to 1.1.1-beta-190722
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