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Task #5683
closedSTD_LOGIC/STD_ULOGIC processing
Start date:
03/04/2015
Due date:
% Done:
100%
Estimated time:
Detected in build:
svn
Published in build:
0.2.1
Description
The signals of STD_LOGIC/STD_ULOGIC now are modelled as DataType.BOOLEAN variables.
If this is incorrect (in fact, we have 9-sign logic at VHDL), the corresponding processing procedure should be implemented (see corresponding TODOs).
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