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Task #5588

closed

extend HDL test suite

Added by Sergey Smolov almost 10 years ago. Updated over 5 years ago.

Status:
Closed
Priority:
Normal
Assignee:
Sergey Smolov
Category:
Test Suite
Target version:
1.0
Start date:
01/28/2015
Due date:
% Done:

100%

Estimated time:
Detected in build:
master
Published in build:
1.1.1-beta-190722

Description

Extend a set of HDL (Verilog. VHDL) designs that are used as project test suite.

The collection of open-source benchmarks is available here: http://ddd.fit.cvut.cz/prj/Benchmarks/

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 #1

Updated by Sergey Smolov over 9 years ago

  • Subject changed from [project] extend HDL test suite to extend HDL test suite
  • Category set to Test Suite
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 #2

Updated by Sergey Smolov over 9 years ago

Check samples of asynchronous Verilog designs here: async.org.uk

Keywords: Tech report towards asynchronous power management

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 #3

Updated by Sergey Smolov over 9 years ago

Look at synthagate examples coming with Decider.

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 #4

Updated by Sergey Smolov over 8 years ago

  • Target version changed from 0.1 to 0.2
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 #5

Updated by Sergey Smolov about 8 years ago

  • Detected in build changed from svn to master
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 #6

Updated by Sergey Smolov about 7 years ago

  • Target version changed from 0.2 to 1.0
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 #7

Updated by Sergey Smolov about 7 years ago

  • Status changed from New to Resolved
  • % Done changed from 0 to 100

ITC99 designs are added in ab8526a7.
Some perspective benchmarks are stored in the internal sub-project.

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 #8

Updated by Sergey Smolov about 7 years ago

  • Status changed from Resolved to Verified
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 #9

Updated by Sergey Smolov over 5 years ago

  • Status changed from Verified to Closed
  • Published in build set to 1.1.1-beta-190722
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