Icarus Verilog Bugs » History » Revision 2
Revision 1 (Sergey Smolov, 04/27/2018 02:50 PM) → Revision 2/8 (Sergey Smolov, 04/27/2018 02:54 PM)
h1. Icarus Verilog Bugs
The bugs are listed here can be reproduced on tests for Verilog Translator project (so called "ieee-tests").
# test_03_08_01_1.v
<pre>
test_03_08_01_1.v:25: syntax error
test_03_08_01_1.v:27: error: malformed statement
test_03_08_01_1.v:28: syntax error
test_03_08_01_1.v:33: error: malformed statement
test_03_08_01_1.v:34: syntax error
test_03_08_01_1.v:39: error: malformed statement
test_03_08_01_1.v:40: syntax error
</pre>
# test_03_08_01_2.v
<pre>
test_03_08_01_2.v:25: syntax error
test_03_08_01_2.v:27: error: malformed statement
test_03_08_01_2.v:28: syntax error
test_03_08_01_2.v:32: error: malformed statement
test_03_08_01_2.v:33: syntax error
</pre>
# test_03_08_01_7.v
<pre>
test_03_08_01_7.v:25: syntax error
test_03_08_01_7.v:25: error: malformed statement
</pre>
# test_04_03_01_1.v
<pre>
test_04_03_01_1.v:24: sorry: trireg nets not supported.
</pre>
# test_04_03_02_1.v
<pre>
test_04_03_02_1.v:22: syntax error
test_04_03_02_1.v:22: error: invalid module item.
test_04_03_02_1.v:23: syntax error
test_04_03_02_1.v:23: error: invalid module item.
</pre>
# test_04_04_01_1.v
<pre>
test_04_04_01_1.v:22: sorry: trireg nets not supported.
test_04_04_01_1.v:23: sorry: trireg nets not supported.
test_04_04_01_1.v:25: syntax error
test_04_04_01_1.v:25: error: invalid module item.
</pre>
# test_05_02_01_4.v
<pre>
test_05_02_01_4.v:54: error: Unable to bind wire/reg/memory `x' in `test'
test_05_02_01_4.v:58: error: Unable to bind wire/reg/memory `z' in `test'
</pre>
# test_05_03_00_1.v
<pre>
test_05_03_00_1.v:25: warning: choosing typ expression.
</pre>
# test_06_01_03_1.v
<pre>
test_06_01_03_1.v:24: sorry: net delays not supported.
</pre>
# Compile test_07_14_01_1.v
<pre>
test_07_14_01_1.v:25: warning: choosing typ expression.
test_07_14_01_1.v:25: warning: choosing typ expression.
test_07_14_01_1.v:25: warning: choosing typ expression.
test_07_14_01_1.v:26: warning: choosing typ expression.
test_07_14_01_1.v:26: warning: choosing typ expression.
test_07_14_01_1.v:26: warning: choosing typ expression.
</pre>
# test_07_14_01_2.v
<pre>
test_07_14_01_2.v:26: warning: choosing typ expression.
test_07_14_01_2.v:27: warning: choosing typ expression.
</pre>
# test_07_14_02_2_1.v
<pre>
test_07_14_02_2_1.v:25: sorry: trireg nets not supported.
</pre>
# test_07_14_02_2_2.v
<pre>
test_07_14_02_2_2.v:26: sorry: trireg nets not supported.
</pre>
# test_08_06_00_1.v
<pre>
test_08_06_00_1.v:46: syntax error
test_08_06_00_1.v:46: error: syntax error in parameter value assignment list.
test_08_06_00_1.v:46: error: Invalid module instantiation
</pre>
# test_09_02_01_1.v
<pre>
test_09_02_01_1.v:31: error: part select rega[3:5] is reversed.
</pre>
# test_09_03_02_1.v
<pre>
test_09_03_02_1.v:32: tgt-vvp sorry: procedural continuous assignments are not yet fully supported. The RHS of this assignment will only be evaluated once, at the time the assignment statement is executed.
test_09_03_02_1.v:37: tgt-vvp sorry: procedural continuous assignments are not yet fully supported. The RHS of this assignment will only be evaluated once, at the time the assignment statement is executed.
test_09_03_02_1.v:38: tgt-vvp sorry: procedural continuous assignments are not yet fully supported. The RHS of this assignment will only be evaluated once, at the time the assignment statement is executed.
</pre>
# test_09_03_02_2.v
<pre>
test_09_03_02_2.v:33: tgt-vvp sorry: procedural continuous assignments are not yet fully supported. The RHS of this assignment will only be evaluated once, at the time the assignment statement is executed.
</pre>