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Icarus Verilog Bugs

The bugs are listed here can be reproduced on tests for Verilog Translator project (so called "ieee-tests").

  1. test_03_08_01_1.v
    test_03_08_01_1.v:25: syntax error
    test_03_08_01_1.v:27: error: malformed statement
    test_03_08_01_1.v:28: syntax error
    test_03_08_01_1.v:33: error: malformed statement
    test_03_08_01_1.v:34: syntax error
    test_03_08_01_1.v:39: error: malformed statement
    test_03_08_01_1.v:40: syntax error
    

    Cause: attributes for "case" statement branches like "(* full_case, parallel_case *)" are unsupported.
  2. test_03_08_01_2.v
    test_03_08_01_2.v:25: syntax error
    test_03_08_01_2.v:27: error: malformed statement
    test_03_08_01_2.v:28: syntax error
    test_03_08_01_2.v:32: error: malformed statement
    test_03_08_01_2.v:33: syntax error
    

    Cause: attributes for "case" statement branches like "(* full_case *)" are unsupported.
  3. test_03_08_01_6.v
    test_03_08_01_6.v:25: syntax error
    test_03_08_01_6.v:25: error: malformed statement
    

    Cause: attributes for assignments like "a = b + (* mode = "cla" *) c;" are unsupported.
  4. test_03_08_01_7.v
    test_03_08_01_7.v:25: syntax error
    test_03_08_01_7.v:25: error: malformed statement
    

    Cause: attributes for assignments like "a = add (* mode = "cla" *) (b, c);" are unsupported.
  5. test_03_08_01_8.v
    test_03_08_01_8.v:25: syntax error
    test_03_08_01_8.v:25: error: malformed statement
    

    Cause: attributes for assignments like "a = b ? (* no_glitch *) c : d;" are unsupported.
  6. test_04_03_01_1.v
    test_04_03_01_1.v:24: sorry: trireg nets not supported.
    

    Cause: cannot parse "trireg (small) storeit;"
  7. test_04_03_02_1.v
    test_04_03_02_1.v:22: syntax error
    test_04_03_02_1.v:22: error: invalid module item.
    test_04_03_02_1.v:23: syntax error
    test_04_03_02_1.v:23: error: invalid module item.
    

    Cause: cannot parse "tri1 scalared [63:0] bus64;"
  8. test_04_04_01_1.v
    test_04_04_01_1.v:22: sorry: trireg nets not supported.
    test_04_04_01_1.v:23: sorry: trireg nets not supported.
    test_04_04_01_1.v:25: syntax error
    test_04_04_01_1.v:25: error: invalid module item.
    

    Cause: cannot parse "trireg a;"
  9. test_04_09_03_1_1.v
    test_04_09_03_1_1.v:26: sorry: only 1 dimensional arrays are currently supported.
    test_04_09_03_1_1.v:28: sorry: only 1 dimensional arrays are currently supported.
    

    Cause: cannot parse "reg arrayb[7:0][0:255];"
  10. test_04_09_03_1_2.v
    test_04_09_03_1_2.v:26: sorry: only 1 dimensional arrays are currently supported.
    test_04_09_03_1_2.v:28: sorry: only 1 dimensional arrays are currently supported.
    

    Cause: cannot parse "reg arrayb[7:0][0:255];"
  11. test_04_10_03_2.v
    test_04_10_03_2.v:23: syntax error
    test_04_10_03_2.v:23: error: invalid module item.
    test_04_10_03_2.v:24: syntax error
    test_04_10_03_2.v:24: error: invalid module item.
    

    Cause: the "specparam" is unsupported.
  12. test_05_01_14_1.v
    test_05_01_14_1.v:30: error: Array b['sd3:'sd0] cannot be indexed by a range.
    

    Cause: cannot parse "result = {a, b[3:0], w, 3'b101};"
  13. test_05_02_01_4.v
    test_05_02_01_4.v:54: error: Unable to bind wire/reg/memory `x' in `test'
    test_05_02_01_4.v:58: error: Unable to bind wire/reg/memory `z' in `test'
    

    Cause: cannot parse "addr = x;"
  14. test_05_02_02_2.v
    test_05_02_02_2.v:25: sorry: only 1 dimensional arrays are currently supported.
    test_05_02_02_2.v:26: sorry: only 1 dimensional arrays are currently supported.
    

    Cause: cnnot parse "wire threed_array[0:255][0:255][0:7];"
  15. test_05_03_00_1.v
    test_05_03_00_1.v:25: warning: choosing typ expression.
    

    Cause: "parameter val = (32'd 50: 32'd 75: 32'd 100);"
  16. test_06_01_03_1.v
    test_06_01_03_1.v:24: sorry: net delays not supported.
    

    Cause: "wire #10 wireA;"
  17. test_07_14_01_1.v
    test_07_14_01_1.v:25: warning: choosing typ expression.
    test_07_14_01_1.v:25: warning: choosing typ expression.
    test_07_14_01_1.v:25: warning: choosing typ expression.
    test_07_14_01_1.v:26: warning: choosing typ expression.
    test_07_14_01_1.v:26: warning: choosing typ expression.
    test_07_14_01_1.v:26: warning: choosing typ expression.
    

    Cause: "bufif0 #(5:7:9, 8:10:12, 15:18:21) b1 (io1, io2, dir);"
  18. test_07_14_01_2.v
    test_07_14_01_2.v:26: warning: choosing typ expression.
    test_07_14_01_2.v:27: warning: choosing typ expression.
    

    Cause: " #(95:100:105) clk = 1;"
  19. test_07_14_02_2_1.v
    test_07_14_02_2_1.v:25: sorry: trireg nets not supported.
    

    Cause: "trireg ( large ) #(0,0,50) cap1;"
  20. test_07_14_02_2_2.v
    test_07_14_02_2_2.v:26: sorry: trireg nets not supported.
    

    Cause: "trireg ( large ) #(0,0,50) cap1;"
  21. test_08_06_00_1.v
    test_08_06_00_1.v:46: syntax error
    test_08_06_00_1.v:46: error: syntax error in parameter value assignment list.
    test_08_06_00_1.v:46: error: Invalid module instantiation
    *Cause*: "d_edge_ff #p3 d_inst (q, clock, data);" 
    
  22. test_08_07_00_1.v
    test_08_07_00_1.v:30: syntax error
    

    Cause: " ? ?? 01 : ? : 1 ;"
  23. test_09_06_00_1.v
    test_09_06_00_1.v:27: syntax error
    test_09_06_00_1.v:28: error: invalid module item.
    test_09_06_00_1.v:29: syntax error
    test_09_06_00_1.v:29: error: Invalid module instantiation
    test_09_06_00_1.v:30: error: Invalid module instantiation
    test_09_06_00_1.v:31: error: Invalid module instantiation
    test_09_06_00_1.v:34: error: invalid module item.
    test_09_06_00_1.v:35: syntax error
    test_09_06_00_1.v:35: error: Invalid module instantiation
    test_09_06_00_1.v:36: error: Invalid module instantiation
    

    Cause: "begin : mult"
  24. test_09_06_00_2.v
    test_09_06_00_2.v:23: syntax error
    test_09_06_00_2.v:24: error: invalid module item.
    test_09_06_00_2.v:25: syntax error
    test_09_06_00_2.v:25: error: Invalid module instantiation
    test_09_06_00_2.v:26: error: Invalid module instantiation
    test_09_06_00_2.v:29: error: invalid module item.
    test_09_06_00_2.v:30: syntax error
    test_09_06_00_2.v:30: error: Invalid module instantiation
    

    Cause: "begin : count1s"
  25. test_09_07_05_4.v
    test_09_07_05_4.v:33: internal error: NetProc::nex_input not implemented
    

    Cause: "* // equivalent to (c or d)
    x = c ^ d;"
  26. test_09_07_07_1.v
    test_09_07_07_1.v:32: syntax error
    

    Cause: "repeat (-3) @ (posedge clk)"
  27. test_10_03_00_5.v
    test_10_03_00_5.v:44: syntax error
    test_10_03_00_5.v:45: error: malformed statement
    test_10_03_00_5.v:48: syntax error
    test_10_03_00_5.v:49: error: malformed statement
    

    Cause: "begin : posedge(clk)"
  28. test_12_02_00_1.v
    test_12_02_00_1.v:57: error: Range expressions must be constant.
    test_12_02_00_1.v:57       : This MSB expression violates the rule: LOG2(DEPTH)
    

    Cause: "reg [LOG2:0] depth;"
  29. test_12_03_07_1.v
    test_12_03_07_1.v:29: error: Scalar port ``net_r'' has a vectored net declaration [64:1].
    test_12_03_07_1.v:26: error: no wire/reg net_r in module driver.
    test_12_03_07_1.v:33: error: Scalar port ``net_r'' has a vectored net declaration [64:1].
    test_12_03_07_1.v:32: error: no wire/reg net_r in module receiver.
    test_12_03_07_1.v:29: error: Net net_r is not defined in this context.
    test_12_03_07_1.v:36: error: Unable to bind wire/reg/memory `net_r' in `receiver'
    

    Cause:
    26: module driver (net_r);
    27:   output net_r;
    28:   real r;
    29:   wire [64:1] net_r = $realtobits(r);
    30: endmodule
    31: 
    32: module receiver (net_r);
    33:   input net_r;
    34:   wire [64:1] net_r;
    35:   real r;
    36:   initial assign r = $bitstoreal (net_r);
    37: endmodule
    
  30. test_12_04_02_1.v
    test_12_04_02_1.v:46: syntax error
    test_12_04_02_1.v:46: error: invalid module item.
    

    Cause: "else;"
  31. test_14_03_00_1.v
    test_14_03_00_1.v:30: warning: choosing typ expression.
    test_14_03_00_1.v:30: warning: choosing typ expression.
    test_14_03_00_1.v:31: warning: choosing typ expression.
    test_14_03_00_1.v:31: warning: choosing typ expression.
    

    Cause:
    specparam  tRise_clk_q = 45:150:270, tFall_clk_q=60:200:350;
    specparam  tRise_Control = 35:40:45, tFall_control=40:50:65;
    
  32. test_14_03_01_1.v
    test_14_03_01_1.v:29: syntax error
    test_14_03_01_1.v:26: error: syntax error in specify block
    

    Cause:
    (C => Q) = 20;
    (C => Q) = 10:14:20;
    
  33. test_15_05_00_2.v
    test_15_05_00_2.v:58: warning: choosing typ expression.
    test_15_05_00_2.v:58: warning: choosing typ expression.
    test_15_05_00_2.v:59: warning: choosing typ expression.
    test_15_05_00_2.v:59: warning: choosing typ expression.
    

    Cause:
    specparam tPLHc = 4:6:9, tPHLc = 5:8:11;
    specparam tPLHpc = 3:5:6, tPHLpc = 4:7:9;
    
  34. test_15_05_01_3.v
    test_15_05_01_3.v:32: warning: timing checks are not supported and delayed signal "del_CLK" will not be driven.
    test_15_05_01_3.v:32: warning: timing checks are not supported and delayed signal "del_DATA1" will not be driven.
    

    Cause:
    $setuphold (posedge CLK, DATA1, -10, 20,,,, del_CLK, del_DATA1);
    
  35. test_15_05_01_4.v
    test_15_05_01_4.v:30: syntax error
    test_15_05_01_4.v:30: Invalid simple path
    test_15_05_01_4.v:31: warning: timing checks are not supported and delayed signal "dCLK" will not be driven.
    test_15_05_01_4.v:31: warning: timing checks are not supported and delayed signal "dD" will not be driven.
    test_15_05_01_4.v:32: warning: timing checks are not supported and delayed signal "dCLK" will not be driven.
    test_15_05_01_4.v:32: warning: timing checks are not supported and delayed signal "dD" will not be driven.
    

    Cause:
    (CLK = Q) = 6;
    $setuphold (posedge CLK, posedge D, -3,  8, , , , dCLK, dD);
    $setuphold (posedge CLK, negedge D, -7, 13, , , , dCLK, dD);
    
  36. test_15_05_02_3.v
    test_15_05_02_3.v:33: warning: timing checks are not supported and delayed signal "dCP" will not be driven.
    test_15_05_02_3.v:33: warning: timing checks are not supported and delayed signal "dD" will not be driven.
    test_15_05_02_3.v:34: warning: timing checks are not supported and delayed signal "dCP" will not be driven.
    test_15_05_02_3.v:34: warning: timing checks are not supported and delayed signal "dTI" will not be driven.
    test_15_05_02_3.v:35: warning: timing checks are not supported and delayed signal "dCP" will not be driven.
    test_15_05_02_3.v:35: warning: timing checks are not supported and delayed signal "dTE" will not be driven.
    

    Cause:
    $setuphold(posedge CP, D, -10,  20, notifier, ,TE_cond_D,  dCP, dD);
    $setuphold(posedge CP, TI, 20, -10, notifier, ,TE_cond_TI, dCP, dTI);
    $setuphold(posedge CP, TE, -4,   8, notifier, ,DXTI_cond,  dCP, dTE);
    
  37. test_15_07_00_1.v
    test_15_07_00_1.v:29: error: Q is not a valid l-value in DFF.
    test_15_07_00_1.v:26:      : Q is declared here as wire.
    

    Cause:
    module DFF (Q, CLK, DAT);
      input CLK;
      input [7:0] DAT;
      output [7:0] Q;
    
      always @(posedge clk)
        Q = DAT;
      specify
        $setup (DAT, posedge CLK, 10);
      endspecify
    endmodule
    
  38. test_16_02_03_1.v
    test_16_02_03_1.v:25: syntax error
    test_16_02_03_1.v:25: error: invalid module item.
    test_16_02_03_1.v:35: syntax error
    test_16_02_03_1.v:35: error: invalid module item.
    

    Cause:
    22:module clock(clk);
    23:  output clk;
    24:  reg clk;
    25:  specparam dhigh=0, dlow=0;
    26:
    27:  initial clk = 0;
    28:
    29:  always
    30:    begin
    31:      #dhigh clk = 1; // Clock remains low for time dlow
    32:                      // before transitioning to 1
    33:      #dlow  clk = 0; // Clock remains high for time dhigh
    34:                      // before transitioning to 0
    35:    end;
    36:endmodule
    
  39. test_17_02_04_4_1.v
    test_17_02_04_4_1.v:40: syntax error
    test_17_02_04_4_1.v:40: error: malformed statement
    

    Cause:
    code = $fread (mem, fd, , count);
    
  40. test_17_05_01_1.v
    test_17_05_01_1.v:31: syntax error
    test_17_05_01_1.v:31: error: invalid module item.
    test_17_05_01_1.v:34: syntax error
    test_17_05_01_1.v:34: error: invalid module item.
    test_17_05_01_1.v:37: syntax error
    test_17_05_01_1.v:37: error: invalid module item.
    

    Cause:
    $async$and$array (mem, {a1,a2,a3,a4,a5,a6,a7}, {b1,b2,b3});
    
    // is equivalent
    $async$and$array (mem, awire, breg);
    
    // An example of a synchronous system call is as follows
    $sync$or$plane (mem, {a1,a2,a3,a4,a5,a6,a7}, {b1,b2,b3});
    
  41. 17_05_02_1.v
    test_17_05_02_1.v:28: syntax error
    test_17_05_02_1.v:28: error: invalid module item.
    test_17_05_02_1.v:31: syntax error
    test_17_05_02_1.v:31: error: invalid module item.
    

    Cause:
    $async$nor$plane (mem,{a1,a2,a3,a4,a5,a6,a7},{b1,b2,b3});
    
    // An example of a nand plane system call is as follows:
    $sync$nand$plane (mem,{a1,a2,a3,a4,a5,a6,a7}, {b1,b2,b3});
    
  42. test_17_08_00_1.v
    test_17_08_00_1.v:26: error: Scalar port ``net_r'' has a vectored net declaration [64:1].
    test_17_08_00_1.v:31: error: Scalar port ``net_r'' has a vectored net declaration [64:1].
    test_17_08_00_1.v:33: error: Unable to bind wire/reg/memory `net_r' in `receiver'
    

    Cause:
    23: module driver (net_r);
    24:   output net_r;
    25:   real r;
    26:   wire [64:1] net_r = $realtobits (r);
    27: endmodule
    28: 
    29: module receiver (net_r);
    30:   input net_r;
    31:   wire [64:1] net_r;
    32:   real r;
    33:   initial assign r = $bitstoreal (net_r);
    34: endmodule
    

Updated by Sergey Smolov over 2 years ago · 8 revisions