Icarus Verilog Bugs¶

The bugs are listed here can be reproduced on tests for Verilog Translator project (so called "ieee-tests").

1. test_03_08_01_1.v
   

   test_03_08_01_1.v:25: syntax error
   test_03_08_01_1.v:27: error: malformed statement
   test_03_08_01_1.v:28: syntax error
   test_03_08_01_1.v:33: error: malformed statement
   test_03_08_01_1.v:34: syntax error
   test_03_08_01_1.v:39: error: malformed statement
   test_03_08_01_1.v:40: syntax error
   

2. test_03_08_01_7.v
   

   test_03_08_01_7.v:25: syntax error
   test_03_08_01_7.v:25: error: malformed statement
   

3. test_04_03_01_1.v
   

   test_04_03_01_1.v:24: sorry: trireg nets not supported.
   

4. test_04_03_02_1.v
   

   test_04_03_02_1.v:22: syntax error
   test_04_03_02_1.v:22: error: invalid module item.
   test_04_03_02_1.v:23: syntax error
   test_04_03_02_1.v:23: error: invalid module item.
   

5. test_04_04_01_1.v
   

   test_04_04_01_1.v:22: sorry: trireg nets not supported.
   test_04_04_01_1.v:23: sorry: trireg nets not supported.
   test_04_04_01_1.v:25: syntax error
   test_04_04_01_1.v:25: error: invalid module item.
   

6. test_05_02_01_4.v
   

   test_05_02_01_4.v:54: error: Unable to bind wire/reg/memory `x' in `test'
   test_05_02_01_4.v:58: error: Unable to bind wire/reg/memory `z' in `test'
   

7. test_05_03_00_1.v
   

   test_05_03_00_1.v:25: warning: choosing typ expression.
   

8. test_06_01_03_1.v
   

   test_06_01_03_1.v:24: sorry: net delays not supported.
   

9. Compile test_07_14_01_1.v
   

   test_07_14_01_1.v:25: warning: choosing typ expression.
   test_07_14_01_1.v:25: warning: choosing typ expression.
   test_07_14_01_1.v:25: warning: choosing typ expression.
   test_07_14_01_1.v:26: warning: choosing typ expression.
   test_07_14_01_1.v:26: warning: choosing typ expression.
   test_07_14_01_1.v:26: warning: choosing typ expression.
   

10. test_07_14_01_2.v
    

    test_07_14_01_2.v:26: warning: choosing typ expression.
    test_07_14_01_2.v:27: warning: choosing typ expression.
    

11. test_07_14_02_2_1.v
    

    test_07_14_02_2_1.v:25: sorry: trireg nets not supported.
    

12. test_07_14_02_2_2.v
    

    test_07_14_02_2_2.v:26: sorry: trireg nets not supported.
    

13. test_08_06_00_1.v
    

    test_08_06_00_1.v:46: syntax error
    test_08_06_00_1.v:46: error: syntax error in parameter value assignment list.
    test_08_06_00_1.v:46: error: Invalid module instantiation
    

14. test_09_02_01_1.v
    

    test_09_02_01_1.v:31: error: part select rega[3:5] is reversed.
    

15. test_09_03_02_1.v
    

    test_09_03_02_1.v:32: tgt-vvp sorry: procedural continuous assignments are not yet fully supported. The RHS of this assignment will only be evaluated once, at the time the assignment statement is executed.
    test_09_03_02_1.v:37: tgt-vvp sorry: procedural continuous assignments are not yet fully supported. The RHS of this assignment will only be evaluated once, at the time the assignment statement is executed.
    test_09_03_02_1.v:38: tgt-vvp sorry: procedural continuous assignments are not yet fully supported. The RHS of this assignment will only be evaluated once, at the time the assignment statement is executed.
    

16. test_09_03_02_2.v
    

    test_09_03_02_2.v:33: tgt-vvp sorry: procedural continuous assignments are not yet fully supported. The RHS of this assignment will only be evaluated once, at the time the assignment statement is executed.