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RISC-V Instruction Set » History » Version 6

Andrei Tatarnikov, 05/09/2018 04:24 PM

1 1 Alexander Protsenko
h1. RISC-V Instruction Set
2
3 6 Andrei Tatarnikov
{font-weight:bold; background:#ddd}. |/2. *Category* |\2. *RISC-V (Version 2.2)* |\2. *MicroTESK* |
4 2 Alexander Protsenko
{background:#dde}. | *Instructions* | *Amount* | *Instructions* | *Amount* |
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{background:#fcc}. | Arithmetic Logic Unit | ADDI
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SLTI
7
SLTIU
8
XLEN
9
ANDI
10
ORI
11
XORI
12
SRLI
13
SLLI
14
LUI
15
AUIPC
16
ADD
17
SUB
18
SLT
19
SLTU
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AND
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OR
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XOR
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SLL
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SRL
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SRA | 21+ |  | 0+ |
26 3 Alexander Protsenko
{background:#fcc}. | Branch| JAL
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JALR
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BEQ
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BNE
30
BLT
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BLTU
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BGE
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BGEU
34
BGT
35
BGTU
36
BLE
37
BLEU
38
BLT
39
BLTU
40
BGE
41 4 Alexander Protsenko
BGEU | 16 |  | 0+ |
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{background:#ff9}. | Memory Access | LW
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LH
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LHU
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LB
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LBU
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SW
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SH
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SB | 8 |  | 0 |
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{background:#fcc}. | System | CSRRW
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CSRRS
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CSRRC
53
CSRRWI
54
CSRRSI
55
CSRRCI
56
RDCYCLE
57
RDTIME
58
RDINSTRET | 9 |  | 0 |
59 2 Alexander Protsenko
{background:#cfc}. | Other | NOP | 1 | NOP | 1 |
60 5 Alexander Protsenko
{background:#ddd}. | Total: || 65 |  | 1+ |
61 1 Alexander Protsenko
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{background:#cfc}. |100%|
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{background:#ff9}. |50+%|
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{background:#fcc}. |0+%|