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Alexander Protsenko, 11/04/2016 02:50 PM
RISC-V Instruction Set¶
| Category | RISC-V (Version 2.1) | MicroTESK | ||
| Instructions | Amount | Instructions | Amount | |
| Arithmetic Logic Unit | ADDI SLTI SLTIU XLEN ANDI ORI XORI SRLI SLLI LUI AUIPC ADD SUB SLT SLTU AND OR XOR SLL SRL SRA |
21+ | 0+ | |
| Branch | JAL JALR BEQ BNE BLT BLTU BGE BGEU BGT BGTU BLE BLEU BLT BLTU BGE BGEU |
16 | 0+ | |
| Memory Access | LW LH LHU LB LBU SW SH SB |
8 | 0 | |
| System | CSRRW CSRRS CSRRC CSRRWI CSRRSI CSRRCI RDCYCLE RDTIME RDINSTRET |
9 | 0 | |
| Other | NOP | 1 | NOP | 1 |
| Total: | 65 | 1+ | ||
| 100% |
| 50+% |
| 0+% |
Updated by Alexander Protsenko over 7 years ago · 5 revisions