Verilog Translator

The following code contains an error:

module main(clk);
     input clk;
    output RDealer1;
    output RDealer2;

Signals RDealer1, RDealer2, declared as outputs, do not appear in the port list. Veritrans does not handle this as an error.
See VerilogTexas97TestCase#runTest_Blackjack_dp test.
Source code is located in: texas97-tests/Blackjack/dp.v