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Task #7723
closedSupport for module instances in Verilog descriptions
Start date:
11/14/2016
Due date:
% Done:
100%
Estimated time:
Detected in build:
master
Published in build:
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Added by Sergey Smolov over 7 years ago. Updated almost 6 years ago.
100%
The task has been moved to Verilog Translator project.
It is supposed, that Verilog design comes to Retrascope as completely instantiated model.