Project

General

Profile

Actions
Copy link

Task #6431

closed

descriptor for (VHDL) variables & signals

Added by Sergey Smolov about 9 years ago. Updated over 8 years ago.

Status:
Closed
Priority:
Normal
Assignee:
Sergey Smolov
Category:
Engine (Parser)
Target version:
0.1
Start date:
11/13/2015
Due date:
% Done:

100%

Estimated time:
Detected in build:
svn
Published in build:
0.2.1

Description

Implement a descriptor that keeps values of all the attributes of VHDL variable/signal.
All the other auxiliary data that is somehow connected with variable could also be added to this descriptor.

Actions
Copy link

Also available in: Atom PDF