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Task #5688

closed

implement test-to-VHDL printer

Added by Sergey Smolov over 9 years ago. Updated over 9 years ago.

Status:
Closed
Priority:
Normal
Category:
Engine (Printer)
Target version:
Start date:
03/05/2015
Due date:
% Done:

100%

Estimated time:
Detected in build:
svn
Published in build:
20150701

Description

The printer should generate VHDL testbenchs that can be simulated using ModelSim or GHDL simulator.

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